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sram1p1rw cleanup

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This commit is contained in:
David Harris 2022-12-20 02:57:51 -08:00
parent 08234cb1c7
commit 16f3c25cb7
2 changed files with 16 additions and 22 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit e302d3bab41a46ec388691b1d961aa09fe2a4bc4
Subproject commit ee028eb325525148a34420a4ca7959b24220a91e

36
pipelined/src/generic/mem/sram1p1rw.sv
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@ -44,8 +44,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
input logic [(WIDTH-1)/8:0] bwe,
output logic [WIDTH-1:0] dout);
logic [WIDTH-1:0] RAM[DEPTH-1:0];
logic [WIDTH-1:0] RAM[DEPTH-1:0];
// ***************************************************************************
// TRUE SRAM macro
@ -65,29 +64,24 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
// ***************************************************************************
// READ first SRAM model
// ***************************************************************************
end else begin
end else begin: ram
integer i;
if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
// Read
always @(posedge clk)
if(ce) dout <= #1 RAM[addr];
// Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8)
always @(posedge clk)
if (ce & we)
for(i = 0; i < WIDTH/8; i++)
if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
if (ce & we & bwe[WIDTH/8])
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
always @(posedge clk) begin
if(ce) begin
dout <= #1 RAM[addr];
end
end
if(WIDTH >= 8) begin
always @(posedge clk) begin
if(ce) begin
if(we) begin
for(i = 0; i < WIDTH/8; i++)
if(bwe[i])
RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
end
end
end
end
end
endmodule