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Finally fixed the ddr3 mig script to work correclty.

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This commit is contained in:
Ross Thompson 2023-04-14 11:41:51 -05:00
parent 679dc7d73b
commit b5799c896e
1 changed files with 2 additions and 3 deletions
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5
fpga/generator/xlnx_ddr3-ArtyA7.tcl
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@ -10,9 +10,8 @@ set_property board_part $boardName [current_project]
# really just these two lines which change
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
exec ls ../xlnx_ddr3-artya7-mig.prj
exec ls ./IP/$ipName.srcs/sources_1/ip/$ipName
exec cp ../xlnx_ddr3-artya7-mig.prj ./IP/$ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
exec cp ../xlnx_ddr3-artya7-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]