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removed instruction misaligned tests from trap tests, signatures

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This commit is contained in:
Kip Macsai-Goren 2022-05-04 21:18:24 +00:00
parent badbe0840f
commit f36fdf940d
12 changed files with 18 additions and 78 deletions
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10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1,7 +1,4 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
@ -57,10 +54,7 @@
00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0

10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -1,10 +1,7 @@
00000aaa # readback value from writing mie to enable interrupts
0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
00000000 # mtval of ecall (*** defined to be zero for now)
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # scause from instruction addr misaligned fault
8000013a # stval of faulting instruction adress
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000 # stval of faulting instruction address (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
@ -59,10 +56,7 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
0000000b # scause from M mode ecall
00000000 # stval of ecall (*** defined to be zero for now)
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # scause from instruction addr misaligned fault
8000013a # stval of faulting instruction adress
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000 # stval of faulting instruction address (0x0)
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0

10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -1,10 +1,7 @@
00000aaa # readback value from writing mie to enable interrupts
0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
00000000 # mtval of ecall (*** defined to be zero for now)
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # scause from instruction addr misaligned fault
8000013a # stval of faulting instruction adress
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000 # stval of faulting instruction address (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
@ -52,10 +49,7 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
0000000b # scause from M mode ecall
00000000 # stval of ecall (*** defined to be zero for now)
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # scause from instruction addr misaligned fault
8000013a # stval of faulting instruction adress
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000 # stval of faulting instruction address (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
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@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
// test 5.3.1.4 Basic trap tests
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -61,7 +61,6 @@ jal cause_m_ext_interrupt
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
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@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enabl
GOTO_S_MODE
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -73,7 +73,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -70,7 +70,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt

16
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1,11 +1,5 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000
00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000
00000000 # mtval of faulting instruction address (0x0)
@ -117,13 +111,7 @@
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
ffffffff
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000000
00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000
00000000 # mtval of faulting instruction address (0x0)

16
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -5,13 +5,7 @@
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # scause from instruction addr misaligned fault
00000000
800003d2 # stval of faulting instruction adress (0x800003d3)
00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)
@ -121,13 +115,7 @@ ffffffff
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # scause from instruction addr misaligned fault
00000000
800003d2 # stval of faulting instruction adress (0x800003d3)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)

16
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -5,13 +5,7 @@
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # scause from instruction addr misaligned fault
00000000
800003d2 # stval of faulting instruction adress (0x800003d3)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)
@ -107,13 +101,7 @@ ffffffff
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000000 # scause from instruction addr misaligned fault
00000000
800003d2 # stval of faulting instruction adress (0x800003d3)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -61,7 +61,6 @@ jal cause_m_ext_interrupt
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enabl
GOTO_S_MODE
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -73,7 +73,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -40,7 +40,7 @@ WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE
jal cause_instr_addr_misaligned
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -70,7 +70,6 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt