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Ross Thompson
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@ -1,14 +1,17 @@
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///////////////////////////////////////////
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// 1 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Written: ross1728@gmail.com
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// Created: 3 May 2021
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// Modified: 20 January 2023
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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// Basic sram with 1 read write port.
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// When clk rises Addr and LineWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -38,13 +38,13 @@ module bpred (
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input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
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input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
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output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
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output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage.
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output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
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// Update Predictor
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input logic [`XLEN-1:0] PCF, // Fetch stage instruction address.
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input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took.
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input logic [`XLEN-1:0] PCE, // Execution stage instruction address.
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input logic [`XLEN-1:0] PCM, // Memory stage instruction address.
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input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
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input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
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input logic [`XLEN-1:0] PCE, // Execution stage instruction address
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input logic [`XLEN-1:0] PCM, // Memory stage instruction address
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// Branch and jump outcome
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input logic PCSrcE, // Executation stage branch is taken
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@ -53,11 +53,11 @@ module bpred (
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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// Report branch prediction status
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output logic BPPredWrongE, // Prediction is wrong.
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output logic DirPredictionWrongM, // Prediction direction is wrong.
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output logic BTBPredPCWrongM, // Prediction target wrong.
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output logic RASPredPCWrongM, // RAS prediction is wrong.
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output logic PredictionInstrClassWrongM // Class prediction is wrong.
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output logic BPPredWrongE, // Prediction is wrong
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output logic DirPredictionWrongM, // Prediction direction is wrong
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output logic BTBPredPCWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic PredictionInstrClassWrongM // Class prediction is wrong
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);
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logic BTBValidF;
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@ -28,58 +28,65 @@
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`include "wally-config.vh"
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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(* mark_debug = "true" *) output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
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// Command from CPU
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input logic InvalidateICacheM, // Clears all instruction cache valid bits
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input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic [2:0] IFUHBURST,
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(* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
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(* mark_debug = "true" *) output logic [2:0] IFUHSIZE,
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(* mark_debug = "true" *) output logic IFUHWRITE,
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(* mark_debug = "true" *) input logic IFUHREADY,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
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(* mark_debug = "true" *) input logic IFUHREADY, // Bus ready from IFU to EBU
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(* mark_debug = "true" *) output logic IFUHWRITE, // Bus write operation from IFU to EBU
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(* mark_debug = "true" *) output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
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(* mark_debug = "true" *) output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
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(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Fetch stage instruction address
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
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input logic PCSrcE, // Executation stage branch is taken
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input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
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output logic [`XLEN-1:0] PCE, // Execution stage instruction address
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output logic BPPredWrongE, // Prediction is wrong
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// Mem
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output logic CommittedF,
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input logic [`XLEN-1:0] UnalignedPCNextF,
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output logic [`XLEN-1:0] PCNext2F,
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input logic CSRWriteFenceM,
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input logic InvalidateICacheM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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// branch predictor
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output logic [3:0] InstrClassM,
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output logic DirPredictionWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic PredictionInstrClassWrongM,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic InstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, sfencevmaM,
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output logic ITLBMissF, InstrDAPageFaultF,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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output logic CommittedF, // I$ or bus memory operation started, delay interrupts
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input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
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output logic [`XLEN-1:0] PCNext2F, // Selected PC between branch prediction and next valid PC if CSRWriteFence
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output logic [31:0] InstrD, // The decoded instruction in Decode stage
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output logic [31:0] InstrM, // The decoded instruction in Memory stage
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output logic [`XLEN-1:0] PCM, // Memory stage instruction address
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// branch predictor
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic DirPredictionWrongM, // Prediction direction is wrong
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output logic BTBPredPCWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic PredictionInstrClassWrongM, // Class prediction is wrong
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// Faults
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input logic IllegalBaseInstrFaultD, // Illegal non-compressed instruction
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output logic InstrPageFaultF, // Instruction page fault
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output logic IllegalIEUInstrFaultD, // Illegal instruction including compressed
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output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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// mmu management
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input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
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input logic [`XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
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input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
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input logic ITLBWriteF, // Writes PTE and PageType to ITLB
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input logic [`XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
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input logic STATUS_MXR, // Status CSR: make executable page readable
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input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
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input logic STATUS_MPRV, // Status CSR: modify machine privilege
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input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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output logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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);
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
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logic BranchMisalignedFaultE;
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@ -34,7 +34,7 @@
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation.
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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@ -53,7 +53,7 @@ module lsu (
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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// fpu
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input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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@ -126,7 +126,7 @@ module lsu (
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logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE to DTLB
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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