forked from Github_Repos/cvw
some synth fpu optimizations
This commit is contained in:
Katherine Parry
parent
a0d6f948b8
commit
11b252a735
@ -52,7 +52,7 @@ module fcmp (
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3'b010: CmpNVE = EitherSNaN;//equal
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3'b001: CmpNVE = EitherNaN;//less than
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3'b011: CmpNVE = EitherNaN;//less than or equal
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default: CmpNVE = 1'b0;
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default: CmpNVE = 1'bx;
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endcase
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end
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@ -91,7 +91,7 @@ module fcmp (
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`FMT2:
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if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, XSgnE, {`NE2{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF2]};
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else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
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default: NaNRes = (`FLEN)'(0);
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default: NaNRes = {`FLEN{1'bx}};
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endcase
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else if (`FPSIZES == 4)
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@ -24,18 +24,18 @@ module fctrl (
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// FPU Instruction Decoder
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1;
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1;
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else case(OpD)
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_00_000_0_0; // flw
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3'b011: ControlsD = `FCTRLW'b1_0_10_00_000_0_0; // fld
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flw
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3'b011: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // fld
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_00_00_000_0_0; // fsw
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3'b011: ControlsD = `FCTRLW'b0_0_00_00_000_0_0; // fsd
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsw
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3'b011: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsd
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0; // fmsub
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@ -45,29 +45,29 @@ module fctrl (
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7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0; // fadd
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7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0; // fsub
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7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0; // fmul
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_000_1_0; // fdiv
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7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_001_1_0; // fsqrt
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0; // fdiv
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7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0; // fsqrt
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7'b00100??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_000_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_001_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_00_010_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0; // fsgnjx
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_110_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_101_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0; // fmax
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_00_010_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_00_001_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_00_011_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_00_000__0_1; // non-implemented instruction
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0; // fle
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1; // non-implemented instruction
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endcase
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_00_000_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_00_000_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_00_000_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0; // fclass
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else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.w to int reg
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else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.d to int reg
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else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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7'b1101000: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.s.w w->s
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2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.s.wu wu->s
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@ -80,7 +80,7 @@ module fctrl (
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.s s->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.s s->lu
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endcase
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7'b1111000: ControlsD = `FCTRLW'b1_0_00_00_011_0_0; // fmv.w.x to fp reg
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7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.w.x to fp reg
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7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0; // fcvt.s.d
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7'b1101001: case(Rs2D[1:0])
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2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.d.w w->d
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@ -94,11 +94,11 @@ module fctrl (
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2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.d d->l
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2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.d d->lu
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endcase
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_00_011_0_0; // fmv.d.x to fp reg
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7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.d.x to fp reg
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7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0; // fcvt.d.s
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction
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default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
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endcase
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// unswizzle control bits
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@ -133,7 +133,7 @@ module fcvt (
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`FMT: NewBiasToFp = (`NE-1)'(`BIAS);
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`FMT1: NewBiasToFp = (`NE-1)'(`BIAS1);
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`FMT2: NewBiasToFp = (`NE-1)'(`BIAS2);
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default: NewBiasToFp = 1'bx;
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default: NewBiasToFp = {`NE-1{1'bx}};
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endcase
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assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp;
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@ -34,7 +34,8 @@ module flags(
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logic FmaInvalid; // integer invalid flag
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logic DivInvalid; // integer invalid flag
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logic DivByZero;
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logic [`NE-1:0] MaxExp; // the maximum exponent before overflow
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logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
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logic ShiftGtIntSz; // is the shift greater than the the integer size (use ResExp to account for possible roundning "shift")
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///////////////////////////////////////////////////////////////////////////////
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// Flags
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@ -43,56 +44,51 @@ module flags(
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if (`FPSIZES == 1) begin
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assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : {`NE{1'b1}};
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assign ResExpGteMax = &FullResExp[`NE-1:0] | FullResExp[`NE];
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assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64));
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end else if (`FPSIZES == 2) begin
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assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'($unsigned(65)) : (`NE)'($unsigned(33)) :
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OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}};
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assign ResExpGteMax = OutFmt ? &FullResExp[`NE-1:0] | FullResExp[`NE] : &FullResExp[`NE1-1:0] | (|FullResExp[`NE:`NE1]);
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assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64));
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end else if (`FPSIZES == 3) begin
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logic [`NE-1:0] MaxExpFp;
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always_comb
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case (OutFmt)
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`FMT: begin
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MaxExpFp = {`NE{1'b1}};
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end
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`FMT1: begin
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MaxExpFp = {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}};
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end
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`FMT2: begin
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MaxExpFp = {{`NE-`NE2{1'b0}}, {`NE2{1'b1}}};
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end
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default: begin
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MaxExpFp = 1'bx;
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end
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`FMT: ResExpGteMax = &FullResExp[`NE-1:0] | FullResExp[`NE];
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`FMT1: ResExpGteMax = &FullResExp[`NE1-1:0] | (|FullResExp[`NE:`NE1]);
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`FMT2: ResExpGteMax = &FullResExp[`NE2-1:0] | (|FullResExp[`NE:`NE2]);
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default: ResExpGteMax = 1'bx;
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endcase
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assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp;
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assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64));
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end else if (`FPSIZES == 4) begin
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logic [`NE-1:0] MaxExpFp;
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always_comb
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case (OutFmt)
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2'h3: begin
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MaxExpFp = {`Q_NE{1'b1}};
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end
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2'h1: begin
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MaxExpFp = {{`Q_NE-`D_NE{1'b0}}, {`D_NE{1'b1}}};
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end
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2'h0: begin
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MaxExpFp = {{`Q_NE-`S_NE{1'b0}}, {`S_NE{1'b1}}};
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end
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2'h2: begin
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MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}};
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end
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`Q_FMT: ResExpGteMax = &FullResExp[`Q_NE-1:0] | FullResExp[`Q_NE];
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`D_FMT: ResExpGteMax = &FullResExp[`D_NE-1:0] | (|FullResExp[`Q_NE:`D_NE]);
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`S_FMT: ResExpGteMax = &FullResExp[`S_NE-1:0] | (|FullResExp[`Q_NE:`S_NE]);
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`H_FMT: ResExpGteMax = &FullResExp[`H_NE-1:0] | (|FullResExp[`Q_NE:`H_NE]);
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endcase
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assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp;
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// a left shift of intlen+1 is still in range but any more than that is an overflow
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// inital: | 64 0's | XLEN |
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// | 64 0's | XLEN | << 64
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// | XLEN | 00000... |
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// 65 = ...0 0 0 0 0 1 0 0 0 0 0 1
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// | or | | or |
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// 33 = ...0 0 0 0 0 0 1 0 0 0 0 1
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// | or | | or |
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// larger or equal if:
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// - any of the bits after the most significan 1 is one
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// - the most signifcant in 65 or 33 is still a one in the number and
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// one of the later bits is one
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assign ShiftGtIntSz = (|FullResExp[`Q_NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64));
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end
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// if the result is greater than or equal to the max exponent
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// | and the exponent isn't negitive
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// | | if the input isnt infinity or NaN
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// | | |
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assign Overflow = (FullResExp>={2'b0, MaxExp}) & ~FullResExp[`NE+1]&~(InfIn|NaNIn);
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// if the result is greater than or equal to the max exponent(not taking into account sign)
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// | and the exponent isn't negitive
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// | | if the input isnt infinity or NaN
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// | | |
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assign Overflow = ResExpGteMax & ~FullResExp[`NE+1]&~(InfIn|NaNIn);
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// detecting tininess after rounding
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// the exponent is negitive
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@ -123,12 +119,12 @@ module flags(
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// if the input is NaN or infinity
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// | if the integer res overflows (out of range)
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// | | if the input was negitive but ouputing to a unsigned number
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// | | | the res doesn't round to zero
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// | | | | or the res rounds up out of bounds
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// | | | | and the res didn't underflow
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// | | | | |
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assign IntInvalid = XNaNM|XInfM|Overflow|((XSgnM&~Signed)&(~((CvtCalcExpM[`NE]|(~|CvtCalcExpM))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]);
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// | | if the input was negitive but ouputing to a unsigned number
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// | | | the res doesn't round to zero
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// | | | | or the res rounds up out of bounds
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// | | | | and the res didn't underflow
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// | | | | |
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assign IntInvalid = XNaNM|XInfM|(ShiftGtIntSz&~FullResExp[`NE+1])|((XSgnM&~Signed)&(~((CvtCalcExpM[`NE]|(~|CvtCalcExpM))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]);
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// |
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// or when the positive res rounds up out of range
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assign SigNaN = (XSNaNM&~(IntToFp&CvtOp)) | (YSNaNM&~CvtOp) | (ZSNaNM&FmaOp);
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@ -25,7 +25,7 @@ module fmashiftcalc(
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assign SumZero = ~(|SumM);
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// calculate the sum's exponent
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assign NormSumExp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, FmaNormCntM} + 1 - (`NE+2)'(`NF+4));
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assign NormSumExp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -{{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, FmaNormCntM} - 1 + (`NE+2)'(`NF+4);
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//convert the sum's exponent into the propper percision
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if (`FPSIZES == 1) begin
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@ -40,7 +40,7 @@ module fmashiftcalc(
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`FMT: ConvNormSumExp = NormSumExp;
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`FMT1: ConvNormSumExp = (NormSumExp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|NormSumExp}};
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`FMT2: ConvNormSumExp = (NormSumExp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS2))&{`NE+2{|NormSumExp}};
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default: ConvNormSumExp = `NE+2'bx;
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default: ConvNormSumExp = {`NE+2{1'bx}};
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endcase
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end
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@ -46,7 +46,7 @@ module fsgninj (
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//
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// calculate the result's sign
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assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]);
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assign ResSgn = (SgnOpCodeE[1] ? XSgnE : SgnOpCodeE[0]) ^ YSgnE;
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// format final result based on precision
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// - uses NaN-blocking format
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@ -64,7 +64,7 @@ module fsgninj (
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`FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]};
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`FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]};
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`FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]};
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default: SgnResE = 0;
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default: SgnResE = {`FLEN{1'bx}};
|
||||
endcase
|
||||
|
||||
else if (`FPSIZES == 4)
|
||||
|
||||
@ -82,7 +82,7 @@ module postprocess(
|
||||
logic PreResultDenorm; // is the result denormalized - calculated before LZA corection
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||||
logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count
|
||||
logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count
|
||||
logic [3*`NF+8:0] ShiftIn; // is the sum zero
|
||||
logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero
|
||||
logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result
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||||
logic Plus1; // add one to the final result?
|
||||
logic IntInvalid, Overflow, Underflow, Invalid; // flags
|
||||
@ -150,8 +150,8 @@ module postprocess(
|
||||
ShiftIn = 0;//{{`NORMSHIFTSZ-(3*`NF+8){1'b0}}, DivShiftIn};
|
||||
end
|
||||
default: begin
|
||||
ShiftAmt = 0;
|
||||
ShiftIn = 0;
|
||||
ShiftAmt = {$clog2(`NORMSHIFTSZ){1'bx}};
|
||||
ShiftIn = {`NORMSHIFTSZ{1'bx}};
|
||||
end
|
||||
endcase
|
||||
|
||||
|
||||
@ -98,7 +98,7 @@ module unpackinput (
|
||||
`FMT: BadNaNBox = 0;
|
||||
`FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1];
|
||||
`FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2];
|
||||
default: BadNaNBox = 0;
|
||||
default: BadNaNBox = 1'bx;
|
||||
endcase
|
||||
|
||||
// extract the sign bit
|
||||
@ -107,7 +107,7 @@ module unpackinput (
|
||||
`FMT: Sgn = In[`FLEN-1];
|
||||
`FMT1: Sgn = In[`LEN1-1];
|
||||
`FMT2: Sgn = In[`LEN2-1];
|
||||
default: Sgn = 0;
|
||||
default: Sgn = 1'bx;
|
||||
endcase
|
||||
|
||||
// extract the fraction
|
||||
@ -116,7 +116,7 @@ module unpackinput (
|
||||
`FMT: Frac = In[`NF-1:0];
|
||||
`FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)};
|
||||
`FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)};
|
||||
default: Frac = 0;
|
||||
default: Frac = {`NF{1'bx}};
|
||||
endcase
|
||||
|
||||
// is the exponent non-zero
|
||||
@ -125,7 +125,7 @@ module unpackinput (
|
||||
`FMT: ExpNonZero = |In[`FLEN-2:`NF]; // if input is largest precision (`FLEN - ie quad or double)
|
||||
`FMT1: ExpNonZero = |In[`LEN1-2:`NF1]; // if input is larger precsion (`LEN1 - double or single)
|
||||
`FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half)
|
||||
default: ExpNonZero = 0;
|
||||
default: ExpNonZero = 1'bx;
|
||||
endcase
|
||||
|
||||
// example double to single conversion:
|
||||
@ -142,7 +142,7 @@ module unpackinput (
|
||||
`FMT: Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};
|
||||
`FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero};
|
||||
`FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero};
|
||||
default: Exp = 0;
|
||||
default: Exp = {`NE{1'bx}};
|
||||
endcase
|
||||
|
||||
// is the exponent all 1's
|
||||
@ -151,7 +151,7 @@ module unpackinput (
|
||||
`FMT: ExpMax = &In[`FLEN-2:`NF];
|
||||
`FMT1: ExpMax = &In[`LEN1-2:`NF1];
|
||||
`FMT2: ExpMax = &In[`LEN2-2:`NF2];
|
||||
default: ExpMax = 0;
|
||||
default: ExpMax = 1'bx;
|
||||
endcase
|
||||
|
||||
end else if (`FPSIZES == 4) begin // if all precsisons are supported - quad, double, single, and half
|
||||
|
||||
Loading…
Reference in New Issue
Block a user