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Extended sim time to fully boot Linux. Added comments to hazard unit

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This commit is contained in:
David Harris 2022-04-24 13:51:00 +00:00
parent 08d4c29724
commit 04b0579b89
2 changed files with 3 additions and 3 deletions
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2
pipelined/regression/wally-pipelined.do
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@ -58,7 +58,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
#run 100 ns
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
#force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
run 13000 ms
run 14000 ms
#add log -recursive /*
#do linux-wave.do
#run -all

4
pipelined/src/hazard/hazard.sv
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@ -79,8 +79,8 @@ module hazard(
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign FlushF = BPPredWrongE | InvalidateICacheM;
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** does RetM only need to flush if the privilege changes?
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** why is BPPredWrongE here, but not needed in simple processor
assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM;
// on Trap the memory stage should be flushed going into the W stage,
// except if the instruction causing the Trap is an ecall or ebreak.