forked from Github_Repos/cvw
Fixed batch mode regression test to work with hpmc loggic.
Added logic to exclude the embench warmups from preformance counters.
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@ -81,11 +81,11 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
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#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
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#vsim -coverage -lib work_$2 workopt_$2
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do wave.do
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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run -all
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@ -406,7 +406,7 @@ logic [3:0] dummy;
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logic StartSampleFirst;
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logic StartSampleDelayed;
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logic StartSample;
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logic EndSample;
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logic EndSample, EndSampleFirst, EndSampleDelayed;
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logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
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logic [`XLEN-1:0] FinalHPMCOUNTERH[`COUNTERS-1:0];
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@ -436,11 +436,27 @@ logic [3:0] dummy;
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"Exception",
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"Divide Cycles"
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};
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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// default start condiction is reset
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// default end condiction is end of test (DCacheFlushDone)
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assign StartSampleFirst = InReset;
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end
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always @(negedge clk) begin
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if(StartSample) begin
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@ -465,7 +481,7 @@ logic [3:0] dummy;
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// track the current function or global label
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if (DEBUG == 1) begin : FunctionName
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if (DEBUG == 1 | (`PrintHPMCounters & `ZICOUNTERS_SUPPORTED)) begin : FunctionName
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FunctionName FunctionName(.reset(reset),
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.clk(clk),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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