forked from Github_Repos/cvw
Fixed LSU typos
This commit is contained in:
parent
46f30d3dbe
commit
27cca2e3fd
@ -230,7 +230,7 @@ module lsu (
|
||||
|
||||
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}),
|
||||
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
|
||||
mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM),
|
||||
mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
|
||||
.s(SelUncachedAdr), .y(LSUBusHWDATA));
|
||||
if(CACHE_ENABLED) begin : dcache
|
||||
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
|
||||
|
@ -40,10 +40,10 @@ module subwordwrite (
|
||||
if (`LLEN == 128) begin:sww
|
||||
always_comb
|
||||
case(LSUFunct3M[2:0])
|
||||
2'b000: LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
|
||||
2'b001: LittleEndianWriteDataM = {8{IMAFWriteDataM[15:0]}}; // sh
|
||||
2'b010: LittleEndianWriteDataM = {4{IMAFWriteDataM[31:0]}}; // sw
|
||||
2'b011: LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
|
||||
3'b000: LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
|
||||
3'b001: LittleEndianWriteDataM = {8{IMAFWriteDataM[15:0]}}; // sh
|
||||
3'b010: LittleEndianWriteDataM = {4{IMAFWriteDataM[31:0]}}; // sw
|
||||
3'b011: LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
|
||||
default: LittleEndianWriteDataM = IMAFWriteDataM; // sq
|
||||
endcase
|
||||
end else if (`LLEN == 64) begin:sww
|
||||
|
Loading…
Reference in New Issue
Block a user