forked from Github_Repos/cvw
PPA script progress
This commit is contained in:
David Harris
parent
6fad0dc8ed
commit
1f761c4e06
@ -71,7 +71,7 @@ module comparator #(parameter WIDTH=64) (
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assign flags = {eq, lt, ltu};
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endmodule
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// This comaprator
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// This comaprator is best
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module comparator_dc_flip #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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@ -31,36 +31,318 @@ module ppa_inv(input a, output y);
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endmodule
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*/
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module ppa_add #(parameter WIDTH=8) (
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input logic [7:0] a, b,
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output logic [7:0] y
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module ppa_comparator_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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ppa_comparator #(WIDTH) comp (.*);
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endmodule
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module ppa_comparator #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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logic eq, lt, ltu;
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logic [WIDTH-1:0] af, bf;
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// For signed numbers, flip most significant bit
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assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
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assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
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// behavioral description gives best results
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assign eq = (af == bf);
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assign lt = (af < bf);
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assign flags = {eq, lt};
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endmodule
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module ppa_add_32 #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y
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);
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assign out = a + b;
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assign y = a + b;
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endmodule
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module ppa_add_64 #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y
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);
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assign y = a + b;
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endmodule
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/*module inv4(input logic a, output logic y);
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logic [3:0] b
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INVX2 i0(a, b[0]);
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INVX2 i1(a, b[1]);
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INVX2 i2(a, b[2]);
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INVX2 i3(a, b[3]);
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INVX2 i00(b[0], y;
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INVX2 i01(b[0], y);
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INVX2 i02(b[0], y);
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INVX2 i03(b[0], y);
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INVX2 i10(b[1], y;
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INVX2 i11(b[1], y);
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INVX2 i12(b[1], y);
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INVX2 i13(b[1], y);
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INVX2 i20(b[2], y;
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INVX2 i21(b[2], y);
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INVX2 i22(b[2], y);
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INVX2 i23(b[2], y);
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INVX2 i30(b[3], y;
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INVX2 i31(b[3], y);
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INVX2 i32(b[3], y);
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INVX2 i33(b[3], y);
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module ppa_add_16 #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y
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);
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assign y = a + b;
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endmodule
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*/
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module ppa_shiftleft(
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assign y = a << amt;
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)
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module ppa_mult(
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assign y = a * b;
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)
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module ppa_alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic Carry, Neg;
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logic LT, LTU;
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logic W64, SubArith, ALUOp;
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logic [2:0] ALUFunct;
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logic Asign, Bsign;
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// Extract control signals
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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// SubArith indicates subtraction
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// ALUOp = 0 for address generation addition or 1 for regular ALU
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assign {W64, SubArith, ALUOp} = ALUControl;
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// addition
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
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// condition code flags based on subtract output Sum = A-B
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A
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assign Neg = Sum[WIDTH-1];
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
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always_comb
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casez (ALUFunct)
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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// support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
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if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign Result = FullResult;
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endmodule
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module ppa_shifter (
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input logic [`XLEN-1:0] A,
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input logic [`LOG_XLEN-1:0] Amt,
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input logic Right, Arith, W64,
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output logic [`XLEN-1:0] Y);
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logic [2*`XLEN-2:0] z, zshift;
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logic [`LOG_XLEN-1:0] amttrunc, offset;
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// Handle left and right shifts with a funnel shifter.
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// For RV32, only 32-bit shifts are needed.
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// For RV64, 32 and 64-bit shifts are needed, with sign extension.
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// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
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if (`XLEN==32) begin:shifter // RV32
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always_comb // funnel mux
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if (Right)
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if (Arith) z = {{31{A[31]}}, A};
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else z = {31'b0, A};
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else z = {A, 31'b0};
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assign amttrunc = Amt; // shift amount
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end else begin:shifter // RV64
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always_comb // funnel mux
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if (W64) begin // 32-bit shifts
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if (Right)
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if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
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else z = {95'b0, A[31:0]};
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else z = {32'b0, A[31:0], 63'b0};
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end else begin
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if (Right)
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if (Arith) z = {{63{A[63]}}, A};
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else z = {63'b0, A};
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else z = {A, 63'b0};
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end
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assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
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end
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// opposite offset for right shfits
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assign offset = Right ? amttrunc : ~amttrunc;
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// funnel operation
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assign zshift = z >> offset;
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assign Y = zshift[`XLEN-1:0];
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endmodule
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module ppa_prioritythermometer #(parameter N = 8) (
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input logic [N-1:0] a,
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output logic [N-1:0] y
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);
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// Carefully crafted so design compiler will synthesize into a fast tree structure
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// Rather than linear.
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// create thermometer code mask
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genvar i;
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assign y[0] = ~a[0];
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for (i=1; i<N; i++) begin:therm
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assign y[i] = y[i-1] & ~a[i];
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end
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endmodule
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module ppa_priorityonehot #(parameter N = 8) (
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input logic [N-1:0] a,
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output logic [N-1:0] y
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);
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logic [N-1:0] nolower;
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// create thermometer code mask
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ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
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assign y = a & nolower;
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endmodule
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module ppa_prioriyencoder #(parameter N = 8) (
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input logic [N-1:0] a,
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output logic [$clog2(N)-1:0] y
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);
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// Carefully crafted so design compiler will synthesize into a fast tree structure
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// Rather than linear.
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// create thermometer code mask
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genvar i;
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for (i=0; i<N; i++) begin:pri
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if (a[i]) y= i;
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end
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endmodule
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module decoder
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input logic [$clog2(N)-1:0] a,
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output logic [N-1:0] y
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always_comb begin
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y = 0;
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y[a] = 1;
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end
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module mux3 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? d2 : (s[0] ? d1 : d0);
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endmodule
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module mux4 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
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endmodule
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module mux6 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
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endmodule
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module mux8 #(parameter WIDTH = 8) ( *** add inputs
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input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
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endmodule
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// *** some way to express data-critical inputs
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module flop #(parameter WIDTH = 8) (
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input logic clk,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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q <= #1 d;
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endmodule
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module flopr #(parameter WIDTH = 8) (
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input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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if (reset) q <= #1 0;
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else q <= #1 d;
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endmodule
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module floprasynnc #(parameter WIDTH = 8) (
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input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk or posedge reset)
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if (reset) q <= #1 0;
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else q <= #1 d;
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endmodule
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module flopenr #(parameter WIDTH = 8) (
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input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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if (reset) q <= #1 0;
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else if (en) q <= #1 d;
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endmodule
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28
synthDC/ppa
Executable file
28
synthDC/ppa
Executable file
@ -0,0 +1,28 @@
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#!/bin/bash
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# David_Harris@hmc.edu and Madeleine Masser-Frye 11 May 2022
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# Run PPA experiments on different modules
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rm -rf runs/ppa*
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make synth DESIGN=ppa_add_16 TECH=sky90 DRIVE=INV FREQ=10 MAXOPT=1 &
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make synth DESIGN=ppa_add_32 TECH=sky90 DRIVE=INV FREQ=1 MAXOPT=10 &
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make synth DESIGN=ppa_add_64 TECH=sky90 DRIVE=INV FREQ=10 MAXOPT=1 &
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make synth DESIGN=ppa_add_16 TECH=sky90 DRIVE=INV FREQ=4000 MAXOPT=1 &
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make synth DESIGN=ppa_add_32 TECH=sky90 DRIVE=INV FREQ=4000 MAXOPT=1 &
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make synth DESIGN=ppa_add_64 TECH=sky90 DRIVE=INV FREQ=4000 MAXOPT=1 &
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make synth DESIGN=ppa_add_16 TECH=sky90 DRIVE=INV FREQ=5000 MAXOPT=1 &
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make synth DESIGN=ppa_add_32 TECH=sky90 DRIVE=INV FREQ=5000 MAXOPT=1 &
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make synth DESIGN=ppa_add_64 TECH=sky90 DRIVE=INV FREQ=5000 MAXOPT=1 &
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make synth DESIGN=ppa_add_16 TECH=sky90 DRIVE=INV FREQ=6000 MAXOPT=1 &
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make synth DESIGN=ppa_add_32 TECH=sky90 DRIVE=INV FREQ=6000 MAXOPT=1 &
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make synth DESIGN=ppa_add_64 TECH=sky90 DRIVE=INV FREQ=6000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_16 TECH=sky90 DRIVE=INV FREQ=10 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_32 TECH=sky90 DRIVE=INV FREQ=10 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_64 TECH=sky90 DRIVE=INV FREQ=10 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_16 TECH=sky90 DRIVE=INV FREQ=8000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_32 TECH=sky90 DRIVE=INV FREQ=8000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_64 TECH=sky90 DRIVE=INV FREQ=8000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_16 TECH=sky90 DRIVE=INV FREQ=10000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_32 TECH=sky90 DRIVE=INV FREQ=10000 MAXOPT=1 &
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make synth DESIGN=ppa_comparator_64 TECH=sky90 DRIVE=INV FREQ=10000 MAXOPT=1 &
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wait
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grep "Critical Path Length" runs/ppa_*/reports/*qor*
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grep "Design Area" runs/ppa_*/reports/*qor*
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@ -120,8 +120,8 @@ if {$tech == "sky130"} {
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}
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# Set input/output delay
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set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.1 -max -clock $my_clk [all_outputs]
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set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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# Setting load constraint on output ports
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if {$tech == "sky130"} {
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