Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

Browse Source
This commit is contained in:
Ross Thompson 2022-10-04 17:39:26 -05:00
commit 9e2cfadd7d
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
fpga/constraints/constraints.xdc
View File

@ -35,12 +35,14 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por
##### UART #####
set_property PACKAGE_PIN AW25 [get_ports UARTSin]
set_property PACKAGE_PIN BB21 [get_ports UARTSout]
#set_property PACKAGE_PIN AW25 [get_ports UARTSin]
set_property PACKAGE_PIN R29 [get_ports UARTSin]
#set_property PACKAGE_PIN BB21 [get_ports UARTSout]
set_property PACKAGE_PIN M31 [get_ports UARTSout]
set_max_delay -from [get_ports UARTSin] 10.000
set_max_delay -to [get_ports UARTSout] 10.000
set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
set_property IOSTANDARD LVCMOS12 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS12 [get_ports UARTSout]
set_property DRIVE 6 [get_ports UARTSout]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]