forked from Github_Repos/cvw
Merge pull request #15 from ross144/main
Updates to FPGA synthesis flow and removal of debug markers
This commit is contained in:
Mike Thompson
GitHub
commit
1fed4b16cc
1
.gitignore
vendored
1
.gitignore
vendored
@ -128,3 +128,4 @@ tests/custom/crt0/*.a
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/pipelined/regression/sd_model.log
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fpga/src/sdc/*
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fpga/src/sdc.tar.gz
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fpga/src/CopiedFiles_do_not_add_to_repo/*
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@ -87,7 +87,7 @@ connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe16]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
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connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[63]} ]]
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connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
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create_debug_port u_ila_0 probe
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@ -356,7 +356,7 @@ connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/St
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe69]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
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connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause08_in]]
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connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe70]
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@ -434,9 +434,10 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
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connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe84]
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set_property port_width 53 [get_debug_ports u_ila_0/probe84]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
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connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[63]}]]
|
||||
connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
|
||||
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
@ -531,7 +532,7 @@ connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe102]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.spillsupport/CurrState[0] ]]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
@ -674,7 +675,7 @@ connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe130]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
|
||||
connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[63]} ]]
|
||||
connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe131]
|
||||
@ -1143,8 +1144,3 @@ set_property port_width 53 [get_debug_ports u_ila_0/probe223]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223]
|
||||
connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 53 [get_debug_ports u_ila_0/probe224]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224]
|
||||
connect_debug_port u_ila_0/probe224 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
|
||||
|
||||
|
||||
132
fpga/constraints/marked_debug.txt
Normal file
132
fpga/constraints/marked_debug.txt
Normal file
@ -0,0 +1,132 @@
|
||||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic WriteDataM
|
||||
lsu/lsu.sv: logic LSUHADDR
|
||||
lsu/lsu.sv: logic HRDATA
|
||||
lsu/lsu.sv: logic LSUHWDATA
|
||||
lsu/lsu.sv: logic LSUHREADY
|
||||
lsu/lsu.sv: logic LSUHWRITE
|
||||
lsu/lsu.sv: logic LSUHSIZE
|
||||
lsu/lsu.sv: logic LSUHBURST
|
||||
lsu/lsu.sv: logic LSUHTRANS
|
||||
lsu/lsu.sv: logic LSUHWSTRB
|
||||
lsu/lsu.sv: logic IHAdrM
|
||||
ieu/regfile.sv: logic rf
|
||||
ieu/datapath.sv: logic RegWriteW
|
||||
hazard/hazard.sv: logic BPPredWrongE
|
||||
hazard/hazard.sv: logic LoadStallD
|
||||
hazard/hazard.sv: logic LSUStallM
|
||||
hazard/hazard.sv: logic FCvtIntStallD
|
||||
hazard/hazard.sv: logic DivBusyE
|
||||
hazard/hazard.sv: logic EcallFaultM
|
||||
hazard/hazard.sv: logic WFIStallM
|
||||
hazard/hazard.sv: logic StallF
|
||||
hazard/hazard.sv: logic FlushD
|
||||
cache/cachefsm.sv: statetype CurrState
|
||||
wally/wallypipelinedcore.sv: logic TrapM
|
||||
wally/wallypipelinedcore.sv: logic SrcAM
|
||||
wally/wallypipelinedcore.sv: logic InstrM
|
||||
wally/wallypipelinedcore.sv: logic PCM
|
||||
wally/wallypipelinedcore.sv: logic MemRWM
|
||||
wally/wallypipelinedcore.sv: logic InstrValidM
|
||||
wally/wallypipelinedcore.sv: logic WriteDataM
|
||||
wally/wallypipelinedcore.sv: logic IEUAdrM
|
||||
ifu/spill.sv: statetype CurrState
|
||||
ifu/ifu.sv: logic IFUStallF
|
||||
ifu/ifu.sv: logic IFUHADDR
|
||||
ifu/ifu.sv: logic HRDATA
|
||||
ifu/ifu.sv: logic IFUHREADY
|
||||
ifu/ifu.sv: logic IFUHWRITE
|
||||
ifu/ifu.sv: logic IFUHSIZE
|
||||
ifu/ifu.sv: logic IFUHBURST
|
||||
ifu/ifu.sv: logic IFUHTRANS
|
||||
ifu/ifu.sv: logic PCF
|
||||
ifu/ifu.sv: logic PCNextF
|
||||
ifu/ifu.sv: logic PCPF
|
||||
ifu/ifu.sv: logic PostSpillInstrRawF
|
||||
mmu/hptw.sv: logic ITLBWriteF
|
||||
mmu/hptw.sv: statetype WalkerState
|
||||
privileged/csrs.sv: logic CSRSReadValM
|
||||
privileged/csrs.sv: logic SEPC_REGW
|
||||
privileged/csrs.sv: logic MIP_REGW
|
||||
privileged/csrs.sv: logic SSCRATCH_REGW
|
||||
privileged/csrs.sv: logic SCAUSE_REGW
|
||||
privileged/csr.sv: logic CSRReadValM
|
||||
privileged/csr.sv: logic CSRSrcM
|
||||
privileged/csr.sv: logic CSRWriteValM
|
||||
privileged/csr.sv: logic MSTATUS_REGW
|
||||
privileged/trap.sv: logic InstrMisalignedFaultM
|
||||
privileged/trap.sv: logic BreakpointFaultM
|
||||
privileged/trap.sv: logic LoadAccessFaultM
|
||||
privileged/trap.sv: logic LoadPageFaultM
|
||||
privileged/trap.sv: logic mretM
|
||||
privileged/trap.sv: logic MIP_REGW
|
||||
privileged/trap.sv: logic PendingIntsM
|
||||
privileged/privileged.sv: logic CSRReadM
|
||||
privileged/privileged.sv: logic InterruptM
|
||||
privileged/csrc.sv: logic HPMCOUNTER_REGW
|
||||
privileged/csri.sv: logic MExtInt
|
||||
privileged/csri.sv: logic MIP_REGW_writeabl
|
||||
privileged/csrm.sv: logic MIP_REGW
|
||||
privileged/csrm.sv: logic MEPC_REGW
|
||||
privileged/csrm.sv: logic MEDELEG_REGW
|
||||
privileged/csrm.sv: logic MIDELEG_REGW
|
||||
privileged/csrm.sv: logic MSCRATCH_REGW
|
||||
privileged/csrm.sv: logic MCAUSE_REGW
|
||||
uncore/uart_apb.sv: logic SIN
|
||||
uncore/uart_apb.sv: logic SOUT
|
||||
uncore/uart_apb.sv: logic OUT1b
|
||||
uncore/uartPC16550D.sv: logic RBR
|
||||
uncore/uartPC16550D.sv: logic FCR
|
||||
uncore/uartPC16550D.sv: logic IER
|
||||
uncore/uartPC16550D.sv: logic MCR
|
||||
uncore/uartPC16550D.sv: logic baudpulse
|
||||
uncore/uartPC16550D.sv: statetype rxstate
|
||||
uncore/uartPC16550D.sv: logic rxfifo
|
||||
uncore/uartPC16550D.sv: logic txfifo
|
||||
uncore/uartPC16550D.sv: logic rxfifohead
|
||||
uncore/uartPC16550D.sv: logic rxfifoentries
|
||||
uncore/uartPC16550D.sv: logic RXBR
|
||||
uncore/uartPC16550D.sv: logic rxtimeoutcnt
|
||||
uncore/uartPC16550D.sv: logic rxparityerr
|
||||
uncore/uartPC16550D.sv: logic rxdataready
|
||||
uncore/uartPC16550D.sv: logic rxfifoempty
|
||||
uncore/uartPC16550D.sv: logic rxdata
|
||||
uncore/uartPC16550D.sv: logic RXerrbit
|
||||
uncore/uartPC16550D.sv: logic rxfullbitunwrapped
|
||||
uncore/uartPC16550D.sv: logic txdata
|
||||
uncore/uartPC16550D.sv: logic txnextbit
|
||||
uncore/uartPC16550D.sv: logic txfifoempty
|
||||
uncore/uartPC16550D.sv: logic fifoenabled
|
||||
uncore/uartPC16550D.sv: logic RXerr
|
||||
uncore/uartPC16550D.sv: logic THRE
|
||||
uncore/uartPC16550D.sv: logic rxdataavailintr
|
||||
uncore/uartPC16550D.sv: logic intrID
|
||||
uncore/plic_apb.sv: logic MExtInt
|
||||
uncore/plic_apb.sv: logic Din
|
||||
uncore/plic_apb.sv: logic requests
|
||||
uncore/plic_apb.sv: logic intPriority
|
||||
uncore/plic_apb.sv: logic intInProgress
|
||||
uncore/plic_apb.sv: logic intThreshold
|
||||
uncore/plic_apb.sv: logic intEn
|
||||
uncore/plic_apb.sv: logic intClaim
|
||||
uncore/plic_apb.sv: logic irqMatrix
|
||||
uncore/plic_apb.sv: logic priorities_with_irqs
|
||||
uncore/plic_apb.sv: logic max_priority_with_irqs
|
||||
uncore/plic_apb.sv: logic irqs_at_max_priority
|
||||
uncore/plic_apb.sv: logic threshMask
|
||||
uncore/clint_apb.sv: logic MTIME
|
||||
uncore/clint_apb.sv: logic MTIMECMP
|
||||
ebu/ebu.sv: logic HCLK
|
||||
ebu/ebu.sv: logic HREADY
|
||||
ebu/ebu.sv: logic HRESP
|
||||
ebu/ebu.sv: logic HADDR
|
||||
ebu/ebu.sv: logic HWDATA
|
||||
ebu/ebu.sv: logic HWSTRB
|
||||
ebu/ebu.sv: logic HWRITE
|
||||
ebu/ebu.sv: logic HSIZE
|
||||
ebu/ebu.sv: logic HBURST
|
||||
ebu/ebu.sv: logic HPROT
|
||||
ebu/ebu.sv: logic HTRANS
|
||||
ebu/ebu.sv: logic HMASTLOC
|
||||
ebu/buscachefsm.sv: busstatetype CurrState
|
||||
ebu/busfsm.sv: busstatetype CurrState
|
||||
@ -13,7 +13,7 @@ export board := vcu108
|
||||
|
||||
all: FPGA
|
||||
|
||||
FPGA: IP SDC
|
||||
FPGA: PreProcessFiles IP SDC
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
IP: $(dst)/xlnx_proc_sys_reset.log \
|
||||
@ -25,6 +25,11 @@ SDC:
|
||||
cp $(sdc_src) ../src/
|
||||
tar xzf ../src/sdc.tar.gz -C ../src
|
||||
|
||||
PreProcessFiles:
|
||||
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
|
||||
cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
|
||||
./insert_debug_comment.sh
|
||||
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
cd IP;\
|
||||
|
||||
38
fpga/generator/insert_debug_comment.sh
Executable file
38
fpga/generator/insert_debug_comment.sh
Executable file
@ -0,0 +1,38 @@
|
||||
#!/bin/bash
|
||||
###########################################
|
||||
## insert_debug_comment.sh
|
||||
##
|
||||
## Written: Ross Thompson ross1728@gmail.com
|
||||
## Created: 20 January 2023
|
||||
## Modified: 20 January 2023
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org#licenses#SHL-2.1#
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
# This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo
|
||||
# Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
|
||||
copiedDir="../src/CopiedFiles_do_not_add_to_repo"
|
||||
while read line; do
|
||||
readarray -d ":" -t StrArray <<< "$line"
|
||||
file="${copiedDir}/${StrArray[0]}"
|
||||
signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
|
||||
readarray -d " " -t SigArray <<< $signal
|
||||
sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
|
||||
sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
|
||||
find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g"
|
||||
done < ../constraints/marked_debug.txt
|
||||
@ -15,7 +15,7 @@ read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/x
|
||||
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
|
||||
|
||||
|
||||
read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
|
||||
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
|
||||
read_verilog {../src/fpgaTop.v}
|
||||
read_verilog -sv [glob -type f ../src/sdc/*.sv]
|
||||
|
||||
|
||||
2
pipelined/src/cache/cachefsm.sv
vendored
2
pipelined/src/cache/cachefsm.sv
vendored
@ -85,7 +85,7 @@ module cachefsm (
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_WRITEBACK} statetype;
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
statetype CurrState, NextState;
|
||||
|
||||
assign AMO = CacheAtomic[1] & (&CacheRW);
|
||||
assign StoreAMO = AMO | CacheRW[0];
|
||||
|
||||
@ -67,7 +67,7 @@ module buscachefsm #(
|
||||
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
|
||||
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
||||
|
||||
(* mark_debug = "true" *) busstatetype CurrState, NextState;
|
||||
busstatetype CurrState, NextState;
|
||||
|
||||
logic [AHBWLOGBWPL-1:0] NextBeatCount;
|
||||
logic FinalBeatCount;
|
||||
|
||||
@ -50,7 +50,7 @@ module busfsm (
|
||||
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype;
|
||||
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
||||
|
||||
(* mark_debug = "true" *) busstatetype CurrState, NextState;
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||||
busstatetype CurrState, NextState;
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||||
|
||||
always_ff @(posedge HCLK)
|
||||
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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||||
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||||
@ -52,18 +52,18 @@ module ebu (
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||||
output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
|
||||
|
||||
// AHB-Lite external signals
|
||||
(* mark_debug = "true" *) output logic HCLK, HRESETn,
|
||||
(* mark_debug = "true" *) input logic HREADY, // AHB peripheral ready
|
||||
(* mark_debug = "true" *) input logic HRESP, // AHB peripheral response. 0: OK 1: Error
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
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||||
(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration
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||||
(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
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||||
(* mark_debug = "true" *) output logic HWRITE, // AHB transaction direction after arbitration
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||||
(* mark_debug = "true" *) output logic [2:0] HSIZE, // AHB transaction size after arbitration
|
||||
(* mark_debug = "true" *) output logic [2:0] HBURST, // AHB burst length after arbitration
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||||
(* mark_debug = "true" *) output logic [3:0] HPROT, // AHB protection. Wally does not use
|
||||
(* mark_debug = "true" *) output logic [1:0] HTRANS, // AHB transaction request after arbitration
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||||
(* mark_debug = "true" *) output logic HMASTLOCK // AHB master lock. Wally does not use
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||||
output logic HCLK, HRESETn,
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||||
input logic HREADY, // AHB peripheral ready
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||||
input logic HRESP, // AHB peripheral response. 0: OK 1: Error
|
||||
output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
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||||
output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration
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||||
output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
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||||
output logic HWRITE, // AHB transaction direction after arbitration
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||||
output logic [2:0] HSIZE, // AHB transaction size after arbitration
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||||
output logic [2:0] HBURST, // AHB burst length after arbitration
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||||
output logic [3:0] HPROT, // AHB protection. Wally does not use
|
||||
output logic [1:0] HTRANS, // AHB transaction request after arbitration
|
||||
output logic HMASTLOCK // AHB master lock. Wally does not use
|
||||
);
|
||||
|
||||
typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
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||||
|
||||
@ -28,18 +28,18 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module hazard(
|
||||
module hazard (
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||||
// Detect hazards
|
||||
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
|
||||
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
|
||||
(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
|
||||
(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
|
||||
(* mark_debug = "true" *) input logic DivBusyE, FDivBusyE,
|
||||
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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||||
(* mark_debug = "true" *) input logic WFIStallM,
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||||
input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
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||||
input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
|
||||
input logic LSUStallM, IFUStallF,
|
||||
input logic FCvtIntStallD, FPUStallD,
|
||||
input logic DivBusyE, FDivBusyE,
|
||||
input logic EcallFaultM, BreakpointFaultM,
|
||||
input logic WFIStallM,
|
||||
// Stall & flush outputs
|
||||
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
|
||||
(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
|
||||
output logic StallF, StallD, StallE, StallM, StallW,
|
||||
output logic FlushD, FlushE, FlushM, FlushW
|
||||
);
|
||||
|
||||
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
|
||||
|
||||
@ -57,7 +57,7 @@ module datapath (
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||||
output logic [`XLEN-1:0] WriteDataM, // Write data in Memory stage
|
||||
// Writeback stage signals
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||||
input logic StallW, FlushW, // Stall, flush Writeback stage
|
||||
(* mark_debug = "true" *) input logic RegWriteW, IntDivW, // Write register file, integer divide instruction
|
||||
input logic RegWriteW, IntDivW, // Write register file, integer divide instruction
|
||||
input logic SquashSCW, // Squash a store conditional when a conflict arose
|
||||
input logic [2:0] ResultSrcW, // Select source of result to write back to register file
|
||||
input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result
|
||||
|
||||
@ -38,7 +38,7 @@ module regfile (
|
||||
|
||||
localparam NUMREGS = `E_SUPPORTED ? 16 : 32; // only 16 registers in E mode
|
||||
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] rf[NUMREGS-1:1];
|
||||
logic [`XLEN-1:0] rf[NUMREGS-1:1];
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||||
integer i;
|
||||
|
||||
// Three ported register file
|
||||
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||||
@ -28,32 +28,32 @@
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||||
`include "wally-config.vh"
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||||
|
||||
module ifu (
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
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||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
(* mark_debug = "true" *) output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
|
||||
// Command from CPU
|
||||
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
||||
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
||||
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
||||
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
||||
// Bus interface
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
|
||||
(* mark_debug = "true" *) input logic IFUHREADY, // Bus ready from IFU to EBU
|
||||
(* mark_debug = "true" *) output logic IFUHWRITE, // Bus write operation from IFU to EBU
|
||||
(* mark_debug = "true" *) output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
|
||||
(* mark_debug = "true" *) output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
|
||||
(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
|
||||
output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
|
||||
input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
|
||||
input logic IFUHREADY, // Bus ready from IFU to EBU
|
||||
output logic IFUHWRITE, // Bus write operation from IFU to EBU
|
||||
output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU
|
||||
output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
|
||||
output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
|
||||
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Fetch stage instruction address
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCF, // Fetch stage instruction address
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
output logic [`XLEN-1:0] PCE, // Execution stage instruction address
|
||||
output logic BPPredWrongE, // Prediction is wrong
|
||||
// Mem
|
||||
// Mem
|
||||
output logic CommittedF, // I$ or bus memory operation started, delay interrupts
|
||||
input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
|
||||
input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
|
||||
output logic [`XLEN-1:0] PCNext2F, // Selected PC between branch prediction and next valid PC if CSRWriteFence
|
||||
output logic [31:0] InstrD, // The decoded instruction in Decode stage
|
||||
output logic [31:0] InstrM, // The decoded instruction in Memory stage
|
||||
@ -91,7 +91,7 @@ module ifu (
|
||||
|
||||
localparam [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
|
||||
logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
|
||||
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||
logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
|
||||
logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill
|
||||
@ -100,14 +100,14 @@ module ifu (
|
||||
logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
|
||||
logic [`XLEN-1:0] PCD; // Decode stage instruction address
|
||||
logic [`XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
|
||||
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // Physical address after address translation
|
||||
logic [`PA_BITS-1:0] PCPF; // Physical address after address translation
|
||||
logic [`XLEN+1:0] PCFExt; //
|
||||
|
||||
logic [31:0] IROMInstrF; // Instruction from the IROM
|
||||
logic [31:0] ICacheInstrF; // Instruction from the I$
|
||||
logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus
|
||||
logic CompressedF; // The fetched instruction is compressed
|
||||
(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||
logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
|
||||
|
||||
logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
|
||||
|
||||
@ -58,7 +58,7 @@ module spill #(
|
||||
logic SpillSaveF;
|
||||
logic [15:0] InstrFirstHalf;
|
||||
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
statetype CurrState, NextState;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// PC logic
|
||||
|
||||
@ -47,8 +47,8 @@ module lsu (
|
||||
output logic DCacheAccess, // D cache memory access for performance counters
|
||||
// address and write data
|
||||
input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
|
||||
output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
|
||||
input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
|
||||
output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU
|
||||
// cpu privilege
|
||||
input logic [1:0] PrivilegeModeW, // Current privilege mode
|
||||
@ -66,15 +66,15 @@ module lsu (
|
||||
output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
|
||||
output logic StoreAmoAccessFaultM, // Store or AMO access fault
|
||||
// connect to ahb
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
|
||||
(* mark_debug = "true" *) input logic LSUHREADY, // Bus ready from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic LSUHWRITE, // Bus write operation from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
|
||||
(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
|
||||
output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
|
||||
input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
|
||||
output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
|
||||
input logic LSUHREADY, // Bus ready from LSU to EBU
|
||||
output logic LSUHWRITE, // Bus write operation from LSU to EBU
|
||||
output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
|
||||
output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
|
||||
output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
|
||||
output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
|
||||
// page table walker
|
||||
input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
|
||||
@ -93,7 +93,7 @@ module lsu (
|
||||
logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
|
||||
logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
|
||||
logic [`PA_BITS-1:0] PAdrM; // Physical memory address
|
||||
(* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
|
||||
logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
|
||||
|
||||
logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
|
||||
logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
|
||||
|
||||
@ -53,7 +53,7 @@ module hptw (
|
||||
input logic DataDAPageFaultM,
|
||||
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
|
||||
output logic [1:0] PageType, // page type to TLBs
|
||||
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
||||
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
||||
output logic [1:0] PreLSURWM,
|
||||
output logic [`XLEN+1:0] IHAdrM,
|
||||
output logic [`XLEN-1:0] IHWriteDataM,
|
||||
@ -67,36 +67,36 @@ module hptw (
|
||||
output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM
|
||||
);
|
||||
|
||||
typedef enum logic [3:0] {L0_ADR, L0_RD,
|
||||
typedef enum logic [3:0] {L0_ADR, L0_RD,
|
||||
L1_ADR, L1_RD,
|
||||
L2_ADR, L2_RD,
|
||||
L3_ADR, L3_RD,
|
||||
LEAF, IDLE, UPDATE_PTE} statetype;
|
||||
|
||||
logic DTLBWalk; // register TLBs translation miss requests
|
||||
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||
logic [`PPN_BITS-1:0] CurrentPPN;
|
||||
logic Executable, Writable, Readable, Valid, PTE_U;
|
||||
logic Misaligned, MegapageMisaligned;
|
||||
logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
|
||||
logic StartWalk;
|
||||
logic TLBMiss;
|
||||
logic PRegEn;
|
||||
logic [1:0] NextPageType;
|
||||
logic [`SVMODE_BITS-1:0] SvMode;
|
||||
logic [`XLEN-1:0] TranslationVAdr;
|
||||
logic [`XLEN-1:0] NextPTE;
|
||||
logic UpdatePTE;
|
||||
logic DAPageFault;
|
||||
logic [`PA_BITS-1:0] HPTWReadAdr;
|
||||
logic SelHPTWAdr;
|
||||
logic [`XLEN+1:0] HPTWAdrExt;
|
||||
logic ITLBMissOrDAFaultF;
|
||||
logic DTLBMissOrDAFaultM;
|
||||
logic [`PA_BITS-1:0] HPTWAdr;
|
||||
logic [1:0] HPTWRW;
|
||||
logic [2:0] HPTWSize; // 32 or 64 bit access
|
||||
(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
|
||||
logic DTLBWalk; // register TLBs translation miss requests
|
||||
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||
logic [`PPN_BITS-1:0] CurrentPPN;
|
||||
logic Executable, Writable, Readable, Valid, PTE_U;
|
||||
logic Misaligned, MegapageMisaligned;
|
||||
logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
|
||||
logic StartWalk;
|
||||
logic TLBMiss;
|
||||
logic PRegEn;
|
||||
logic [1:0] NextPageType;
|
||||
logic [`SVMODE_BITS-1:0] SvMode;
|
||||
logic [`XLEN-1:0] TranslationVAdr;
|
||||
logic [`XLEN-1:0] NextPTE;
|
||||
logic UpdatePTE;
|
||||
logic DAPageFault;
|
||||
logic [`PA_BITS-1:0] HPTWReadAdr;
|
||||
logic SelHPTWAdr;
|
||||
logic [`XLEN+1:0] HPTWAdrExt;
|
||||
logic ITLBMissOrDAFaultF;
|
||||
logic DTLBMissOrDAFaultM;
|
||||
logic [`PA_BITS-1:0] HPTWAdr;
|
||||
logic [1:0] HPTWRW;
|
||||
logic [2:0] HPTWSize; // 32 or 64 bit access
|
||||
statetype WalkerState, NextWalkerState, InitialWalkerState;
|
||||
|
||||
// map hptw access faults onto either the original LSU load/store fault or instruction access fault
|
||||
assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0];
|
||||
|
||||
@ -86,11 +86,11 @@ module csr #(parameter
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] CSRReadValM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] CSRSrcM;
|
||||
logic [`XLEN-1:0] CSRReadValM;
|
||||
logic [`XLEN-1:0] CSRSrcM;
|
||||
logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
|
||||
logic [`XLEN-1:0] CSRWriteValM;
|
||||
logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
|
||||
logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
|
||||
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW;
|
||||
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
|
||||
|
||||
@ -63,7 +63,7 @@ module csrc #(parameter
|
||||
);
|
||||
|
||||
logic [4:0] CounterNumM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
|
||||
logic LoadStallE, LoadStallM;
|
||||
logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
|
||||
|
||||
@ -39,9 +39,9 @@ module csri #(parameter
|
||||
input logic CSRMWriteM, CSRSWriteM,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
input logic [11:0] CSRAdrM,
|
||||
(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
|
||||
input logic MExtInt, SExtInt, MTimerInt, MSwInt,
|
||||
output logic [11:0] MIP_REGW, MIE_REGW,
|
||||
(* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
|
||||
output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
|
||||
);
|
||||
|
||||
logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
|
||||
|
||||
@ -78,12 +78,12 @@ module csrm #(parameter
|
||||
input logic [11:0] CSRAdrM,
|
||||
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW,
|
||||
input logic [11:0] MIP_REGW, MIE_REGW,
|
||||
output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
|
||||
output logic [`XLEN-1:0] MEPC_REGW,
|
||||
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] MEDELEG_REGW,
|
||||
(* mark_debug = "true" *) output logic [11:0] MIDELEG_REGW,
|
||||
output logic [`XLEN-1:0] MEDELEG_REGW,
|
||||
output logic [11:0] MIDELEG_REGW,
|
||||
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
|
||||
output logic WriteMSTATUSM, WriteMSTATUSHM,
|
||||
@ -91,8 +91,8 @@ module csrm #(parameter
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
|
||||
logic [`XLEN-1:0] MSCRATCH_REGW;
|
||||
logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
|
||||
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
|
||||
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
|
||||
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
|
||||
|
||||
@ -42,21 +42,21 @@ module csrs #(parameter
|
||||
STVAL = 12'h143,
|
||||
SIP= 12'h144,
|
||||
SATP = 12'h180) (
|
||||
input logic clk, reset,
|
||||
input logic InstrValidNotFlushedM,
|
||||
input logic CSRSWriteM, STrapM,
|
||||
input logic [11:0] CSRAdrM,
|
||||
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
|
||||
input logic STATUS_TVM,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW,
|
||||
output logic [31:0] SCOUNTEREN_REGW,
|
||||
output logic [`XLEN-1:0] SATP_REGW,
|
||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
|
||||
output logic WriteSSTATUSM,
|
||||
output logic IllegalCSRSAccessM
|
||||
input logic clk, reset,
|
||||
input logic InstrValidNotFlushedM,
|
||||
input logic CSRSWriteM, STrapM,
|
||||
input logic [11:0] CSRAdrM,
|
||||
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
|
||||
input logic STATUS_TVM,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
|
||||
output logic [`XLEN-1:0] SEPC_REGW,
|
||||
output logic [31:0] SCOUNTEREN_REGW,
|
||||
output logic [`XLEN-1:0] SATP_REGW,
|
||||
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
|
||||
output logic WriteSSTATUSM,
|
||||
output logic IllegalCSRSAccessM
|
||||
);
|
||||
|
||||
// Constants
|
||||
@ -66,8 +66,8 @@ module csrs #(parameter
|
||||
logic WriteSTVECM;
|
||||
logic WriteSSCRATCHM, WriteSEPCM;
|
||||
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
|
||||
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
||||
logic [`XLEN-1:0] SCAUSE_REGW;
|
||||
|
||||
// write enables
|
||||
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
|
||||
|
||||
@ -34,7 +34,7 @@ module privileged (
|
||||
input logic StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// CSR Reads and Writes, and values needed for traps
|
||||
(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, // Read or write CSRs
|
||||
input logic CSRReadM, CSRWriteM, // Read or write CSRs
|
||||
input logic [`XLEN-1:0] SrcAM, // GPR register to write
|
||||
input logic [31:0] InstrM, // Instruction
|
||||
input logic [`XLEN-1:0] IEUAdrM, // address from IEU
|
||||
@ -104,7 +104,7 @@ module privileged (
|
||||
logic DelegateM; // trap should be delegated
|
||||
logic wfiM; // wait for interrupt instruction
|
||||
logic IntPendingM; // interrupt is pending, even if not enabled. ends wfi
|
||||
(* mark_debug = "true" *) logic InterruptM; // interrupt occuring
|
||||
logic InterruptM; // interrupt occuring
|
||||
|
||||
|
||||
// track the current privilege level
|
||||
|
||||
@ -30,14 +30,14 @@
|
||||
|
||||
module trap (
|
||||
input logic reset,
|
||||
(* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM,
|
||||
(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
|
||||
(* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources
|
||||
(* mark_debug = "true" *) input logic mretM, sretM, // return instructions
|
||||
input logic InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM,
|
||||
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
|
||||
input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
|
||||
input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources
|
||||
input logic mretM, sretM, // return instructions
|
||||
input logic wfiM, // wait for interrupt instruction
|
||||
input logic [1:0] PrivilegeModeW, // current privilege mode
|
||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs
|
||||
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs
|
||||
input logic [`XLEN-1:0] MEDELEG_REGW, // exception delegation SR
|
||||
input logic STATUS_MIE, STATUS_SIE, // machine/supervisor interrupt enables
|
||||
input logic InstrValidM, // current instruction is valid, not flushed
|
||||
@ -55,7 +55,7 @@ module trap (
|
||||
logic ExceptionM; // exception is occurring
|
||||
logic Committed; // LSU or IFU has committed to a bus operation that can't be interrupted
|
||||
logic BothInstrAccessFaultM; // instruction or HPTW ITLB fill caused an Instruction Access Fault
|
||||
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled
|
||||
logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled
|
||||
|
||||
///////////////////////////////////////////
|
||||
// Determine pending enabled interrupts
|
||||
|
||||
@ -39,14 +39,14 @@ module clint_apb (
|
||||
input logic PENABLE,
|
||||
output logic [`XLEN-1:0] PRDATA,
|
||||
output logic PREADY,
|
||||
(* mark_debug = "true" *) output logic [63:0] MTIME,
|
||||
output logic [63:0] MTIME,
|
||||
output logic MTimerInt, MSwInt
|
||||
);
|
||||
|
||||
logic MSIP;
|
||||
logic [15:0] entry;
|
||||
logic memwrite;
|
||||
(* mark_debug = "true" *) logic [63:0] MTIMECMP;
|
||||
logic [63:0] MTIMECMP;
|
||||
integer i, j;
|
||||
|
||||
assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
|
||||
|
||||
@ -53,27 +53,27 @@ module plic_apb (
|
||||
output logic [`XLEN-1:0] PRDATA,
|
||||
output logic PREADY,
|
||||
input logic UARTIntr,GPIOIntr,
|
||||
(* mark_debug = "true" *) output logic MExtInt, SExtInt
|
||||
output logic MExtInt, SExtInt
|
||||
);
|
||||
|
||||
logic memwrite, memread;
|
||||
logic [23:0] entry;
|
||||
(* mark_debug = "true" *) logic [31:0] Din, Dout;
|
||||
logic [31:0] Din, Dout;
|
||||
|
||||
// context-independent signals
|
||||
(* mark_debug = "true" *) logic [`N:1] requests;
|
||||
(* mark_debug = "true" *) logic [`N:1][2:0] intPriority;
|
||||
(* mark_debug = "true" *) logic [`N:1] intInProgress, intPending, nextIntPending;
|
||||
logic [`N:1] requests;
|
||||
logic [`N:1][2:0] intPriority;
|
||||
logic [`N:1] intInProgress, intPending, nextIntPending;
|
||||
|
||||
// context-dependent signals
|
||||
(* mark_debug = "true" *) logic [`C-1:0][2:0] intThreshold;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][`N:1] intEn;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
|
||||
(* mark_debug = "true" *) logic [`C-1:0][7:1][`N:1] irqMatrix;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][7:1] priorities_with_irqs;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][7:1] max_priority_with_irqs;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][`N:1] irqs_at_max_priority;
|
||||
(* mark_debug = "true" *) logic [`C-1:0][7:1] threshMask;
|
||||
logic [`C-1:0][2:0] intThreshold;
|
||||
logic [`C-1:0][`N:1] intEn;
|
||||
logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
|
||||
logic [`C-1:0][7:1][`N:1] irqMatrix;
|
||||
logic [`C-1:0][7:1] priorities_with_irqs;
|
||||
logic [`C-1:0][7:1] max_priority_with_irqs;
|
||||
logic [`C-1:0][`N:1] irqs_at_max_priority;
|
||||
logic [`C-1:0][7:1] threshMask;
|
||||
|
||||
// =======
|
||||
// AHB I/O
|
||||
|
||||
@ -56,10 +56,10 @@ module uartPC16550D(
|
||||
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
|
||||
|
||||
// Registers
|
||||
(* mark_debug = "true" *) logic [10:0] RBR;
|
||||
(* mark_debug = "true" *) logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
|
||||
(* mark_debug = "true" *) logic [3:0] IER, MSR;
|
||||
(* mark_debug = "true" *) logic [4:0] MCR;
|
||||
logic [10:0] RBR;
|
||||
logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
|
||||
logic [3:0] IER, MSR;
|
||||
logic [4:0] MCR;
|
||||
|
||||
// Syncrhonized and delayed UART signals
|
||||
logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
|
||||
@ -72,50 +72,50 @@ module uartPC16550D(
|
||||
logic DLAB; // Divisor Latch Access Bit (LCR bit 7)
|
||||
|
||||
// Baud and rx/tx timing
|
||||
(* mark_debug = "true" *) logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
|
||||
logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
|
||||
logic [16+`UART_PRESCALE-1:0] baudcount;
|
||||
logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
|
||||
logic [3:0] rxbitsreceived, txbitssent;
|
||||
(* mark_debug = "true" *) statetype rxstate, txstate;
|
||||
statetype rxstate, txstate;
|
||||
|
||||
// shift registrs and FIFOs
|
||||
logic [9:0] rxshiftreg;
|
||||
(* mark_debug = "true" *) logic [10:0] rxfifo[15:0];
|
||||
(* mark_debug = "true" *) logic [7:0] txfifo[15:0];
|
||||
logic [10:0] rxfifo[15:0];
|
||||
logic [7:0] txfifo[15:0];
|
||||
logic [4:0] rxfifotailunwrapped;
|
||||
(* mark_debug = "true" *) logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
|
||||
(* mark_debug = "true" *) logic [3:0] rxfifoentries, txfifoentries;
|
||||
logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
|
||||
logic [3:0] rxfifoentries, txfifoentries;
|
||||
logic [3:0] rxbitsexpected, txbitsexpected;
|
||||
|
||||
// receive data
|
||||
(* mark_debug = "true" *) logic [10:0] RXBR;
|
||||
(* mark_debug = "true" *) logic [9:0] rxtimeoutcnt;
|
||||
logic [10:0] RXBR;
|
||||
logic [9:0] rxtimeoutcnt;
|
||||
logic rxcentered;
|
||||
logic rxparity, rxparitybit, rxstopbit;
|
||||
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
|
||||
(* mark_debug = "true" *) logic rxdataready;
|
||||
(* mark_debug = "true" *) logic rxfifoempty, rxfifotriggered, rxfifotimeout;
|
||||
logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
|
||||
logic rxdataready;
|
||||
logic rxfifoempty, rxfifotriggered, rxfifotimeout;
|
||||
logic rxfifodmaready;
|
||||
logic [8:0] rxdata9;
|
||||
(* mark_debug = "true" *) logic [7:0] rxdata;
|
||||
(* mark_debug = "true" *) logic [15:0] RXerrbit, rxfullbit;
|
||||
(* mark_debug = "true" *) logic [31:0] rxfullbitunwrapped;
|
||||
logic [7:0] rxdata;
|
||||
logic [15:0] RXerrbit, rxfullbit;
|
||||
logic [31:0] rxfullbitunwrapped;
|
||||
|
||||
// transmit data
|
||||
logic [7:0] TXHR, nexttxdata;
|
||||
(* mark_debug = "true" *) logic [11:0] txdata, txsr;
|
||||
(* mark_debug = "true" *) logic txnextbit, txhrfull, txsrfull;
|
||||
logic [11:0] txdata, txsr;
|
||||
logic txnextbit, txhrfull, txsrfull;
|
||||
logic txparity;
|
||||
(* mark_debug = "true" *) logic txfifoempty, txfifofull, txfifodmaready;
|
||||
logic txfifoempty, txfifofull, txfifodmaready;
|
||||
|
||||
// control signals
|
||||
(* mark_debug = "true" *) logic fifoenabled, fifodmamodesel, evenparitysel;
|
||||
logic fifoenabled, fifodmamodesel, evenparitysel;
|
||||
|
||||
// interrupts
|
||||
(* mark_debug = "true" *) logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
|
||||
(* mark_debug = "true" *) logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
|
||||
(* mark_debug = "true" *) logic rxdataavailintr, modemstatusintr, intrpending;
|
||||
(* mark_debug = "true" *) logic [2:0] intrID;
|
||||
logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
|
||||
logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
|
||||
logic rxdataavailintr, modemstatusintr, intrpending;
|
||||
logic [2:0] intrID;
|
||||
|
||||
logic baudpulseComb;
|
||||
logic HeadPointerLastMove;
|
||||
|
||||
@ -40,9 +40,9 @@ module uart_apb (
|
||||
input logic PENABLE,
|
||||
output logic [`XLEN-1:0] PRDATA,
|
||||
output logic PREADY,
|
||||
(* mark_debug = "true" *) input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
|
||||
(* mark_debug = "true" *) output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
|
||||
(* mark_debug = "true" *) output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
|
||||
input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
|
||||
output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
|
||||
output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
|
||||
|
||||
// UART interface signals
|
||||
logic [2:0] entry;
|
||||
|
||||
@ -52,23 +52,23 @@ module wallypipelinedcore (
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
logic FlushD, FlushE, FlushM, FlushW;
|
||||
logic RetM;
|
||||
(* mark_debug = "true" *) logic TrapM;
|
||||
logic TrapM;
|
||||
|
||||
// signals that must connect through DP
|
||||
logic IntDivE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
logic [31:0] InstrD;
|
||||
(* mark_debug = "true" *) logic [31:0] InstrM;
|
||||
logic [31:0] InstrM;
|
||||
logic [`XLEN-1:0] PCF, PCE, PCLinkE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
(* mark_debug = "true" *) logic [1:0] MemRWM;
|
||||
(* mark_debug = "true" *) logic InstrValidM;
|
||||
logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [1:0] MemRWM;
|
||||
logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
@ -110,7 +110,6 @@ module wallypipelinedcore (
|
||||
logic sfencevmaM, WFIStallM;
|
||||
logic SelHPTW;
|
||||
|
||||
|
||||
// PMA checker signals
|
||||
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
@ -122,8 +121,8 @@ module wallypipelinedcore (
|
||||
// cpu lsu interface
|
||||
logic [2:0] Funct3M;
|
||||
logic [`XLEN-1:0] IEUAdrE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
||||
logic [`XLEN-1:0] WriteDataM;
|
||||
logic [`XLEN-1:0] IEUAdrM;
|
||||
logic [`LLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user