fixing port errors

pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.sv

@@ -1 +0,0 @@
-/home/jstine/memory/ts1n28hpcpsvtb64x128m4swbaso_180a/VERILOG/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v

pipelined/src/wally/wallypipelinedsocwrapper.v

@@ -42,6 +42,7 @@ module wallypipelinedsocwrapper (
   output 	     HCLK, HRESETn,
   output [31:0]      HADDR,
   output [`AHBW-1:0] HWDATA,
+  output logic [`XLEN/8-1:0] HWSTRB,
   output 	     HWRITE,
   output [2:0] 	     HSIZE,
   output [2:0] 	     HBURST,

pipelined/testbench/testbench.sv

@@ -55,6 +55,7 @@ logic [3:0] dummy;
   logic             HREADYEXT, HRESPEXT;
   logic [31:0]      HADDR;
   logic [`AHBW-1:0] HWDATA;
+  logic [`XLEN/8-1:0] HWSTRB;
   logic             HWRITE;
   logic [2:0]       HSIZE;
   logic [2:0]       HBURST;
@@ -154,7 +155,7 @@ logic [3:0] dummy;
   assign HRDATAEXT = 0;
 
   wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);