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Initial FDIVSQRT simplification working

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This commit is contained in:
David Harris 2022-08-29 12:01:09 -07:00
parent 16cde5f87e
commit 7b0e43bc10
2 changed files with 8 additions and 6 deletions
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12
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -66,6 +66,7 @@ module fdivsqrtfsm(
//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
logic [`DIVb+3:0] W;
logic SpecialCase;
logic WZeroDelayed; // *** later remove
//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
assign DivBusy = (state == BUSY);
@ -87,7 +88,8 @@ module fdivsqrtfsm(
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
assign DivSE = |W;
end
assign DivDone = (state == DONE);
flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
assign DivDone = (state == DONE) | WZeroDelayed;
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
assign EarlyTermShiftE = step;
@ -102,14 +104,14 @@ module fdivsqrtfsm(
step <= Dur;
if (SpecialCase) state <= #1 DONE;
else state <= #1 BUSY;
end else if (DivDone) begin
if (StallM) state <= #1 DONE;
else state <= #1 IDLE;
end else if (state == BUSY) begin
if ((step == 1) | WZero) begin
if (step == 0) begin
state <= #1 DONE;
end
step <= step - 1;
end else if (state == DONE) begin
if (StallM) state <= #1 DONE;
else state <= #1 IDLE;
end
end
endmodule

2
pipelined/src/fpu/fdivsqrtpreproc.sv
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@ -73,7 +73,7 @@ module fdivsqrtpreproc (
assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
assign Dur = (`DURLEN)'(`FPDUR);
assign Dur = (`DURLEN)'(`FPDUR-1);
// radix 2 radix 4
// 1 copies DIVLEN+2 DIVLEN+2/2