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Merge branch 'main' of github.com:davidharrishmc/riscv-wally

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This commit is contained in:
Ross Thompson 2022-12-27 15:06:25 -06:00
commit 66b2fbd836
7 changed files with 19 additions and 23 deletions
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4
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -82,12 +82,12 @@ module fdivsqrt(
.XNaNE, .YNaNE, .MDUE,
.XInfE, .YInfE, .WZeroE, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, // .SqrtM,
.X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
.IFDivStartE, .FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc(
.clk, .reset, .StallM,
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .MDUE, .Firstun,
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .Firstun,
.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM,
.nM, .ALTBM, .mM, .BZeroM, .AsM, .NegQuotM, .W64M,
.QmM, .WZeroE, .DivSM, .FPIntDivResultM);

13
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -34,8 +34,7 @@ module fdivsqrtiter(
input logic clk,
input logic IFDivStartE,
input logic FDivBusyE,
input logic SqrtE, MDUE,
// input logic SqrtM,
input logic SqrtE,
input logic [`DIVb+3:0] X,
input logic [`DIVb-1:0] DPreproc,
output logic [`DIVb-1:0] D,
@ -78,8 +77,8 @@ module fdivsqrtiter(
// UOTFC Result U and UM registers/initialization mux
// Initialize U to 1.0 and UM to 0 for square root or negative-result int division; U to 0 and UM to -1 otherwise
assign initU = ((SqrtE & ~(MDUE))) ? {1'b1, {(`DIVb){1'b0}}} : 0;
assign initUM = ((SqrtE & ~(MDUE))) ? 0 : {1'b1, {(`DIVb){1'b0}}};
assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0;
assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]);
@ -88,7 +87,7 @@ module fdivsqrtiter(
// C register/initialization mux
// Initialize C to -1 for sqrt and -R for division
logic [1:0] initCUpper;
assign initCUpper = (SqrtE & ~(MDUE)) ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
assign initC = {initCUpper, {`DIVb{1'b0}}};
mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC);
flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
@ -110,13 +109,13 @@ module fdivsqrtiter(
generate
for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
if (`RADIX == 2) begin: stage
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .MDUE,
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end else begin: stage
logic j1;
assign j1 = (i == 0 & ~C[0][`DIVb-1]);
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .MDUE,
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end

5
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -37,7 +37,7 @@ module fdivsqrtpostproc(
input logic [`DIVb-1:0] D,
input logic [`DIVb:0] FirstU, FirstUM,
input logic [`DIVb+1:0] FirstC,
input logic SqrtE, MDUE,
input logic SqrtE,
input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
input logic [`XLEN-1:0] ForwardedSrcAM,
input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
@ -74,8 +74,7 @@ module fdivsqrtpostproc(
assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0}; // F for square root
assign FZeroDivE = {3'b001,D,1'b0}; // F for divide
assign FZeroE = SqrtE ? FZeroSqrtE : FZeroDivE;
// assign FZeroE = (SqrtE & ~MDUE) ? FZeroSqrtE : FZeroDivE;
mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
assign WZeroE = weq0E|(wfeq0E & Firstun);

4
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
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@ -34,7 +34,7 @@ module fdivsqrtqsel4cmp (
input logic [2:0] Dmsbs,
input logic [4:0] Smsbs,
input logic [7:0] WSmsbs, WCmsbs,
input logic SqrtE, j1, MDUE,
input logic SqrtE, j1,
output logic [3:0] udigit
);
logic [6:0] Wmsbs;
@ -72,7 +72,7 @@ module fdivsqrtqsel4cmp (
// Choose A for current operation
always_comb
if (SqrtE & ~MDUE) begin
if (SqrtE) begin
if (j1) A = 3'b101;
else if (Smsbs == 5'b10000) A = 3'b111;
else A = Smsbs[2:0];

5
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -38,7 +38,6 @@ module fdivsqrtstage2 (
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE,
input logic MDUE,
output logic un,
output logic [`DIVb+1:0] CNext,
output logic [`DIVb:0] UNext, UMNext,
@ -73,8 +72,8 @@ module fdivsqrtstage2 (
// Partial Product Generation
// WSA, WCA = WS + WC - qD
assign AddIn = (SqrtE & ~MDUE) ? F : Dsel;
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~(SqrtE & ~MDUE), WSA, WCA);
assign AddIn = SqrtE ? F : Dsel;
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
assign WSNext = WSA << 1;
assign WCNext = WCA << 1;

10
pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -36,7 +36,7 @@ module fdivsqrtstage4 (
input logic [`DIVb:0] U, UM,
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE, j1, MDUE,
input logic SqrtE, j1,
output logic [`DIVb+1:0] CNext,
output logic un,
output logic [`DIVb:0] UNext, UMNext,
@ -65,7 +65,7 @@ module fdivsqrtstage4 (
assign WCmsbs = WC[`DIVb+3:`DIVb-4];
assign WSmsbs = WS[`DIVb+3:`DIVb-4];
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .MDUE);
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
assign un = 1'b0; // unused for radix 4
// F generation logic
@ -84,8 +84,8 @@ module fdivsqrtstage4 (
// Residual Update
// {WS, WC}}Next = (WS + WC - qD or F) << 2
assign AddIn = (SqrtE & ~MDUE) ? F : Dsel;
assign CarryIn = ~(SqrtE & ~MDUE) & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D
assign AddIn = SqrtE ? F : Dsel;
assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D
csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
assign WSNext = WSA << 2;
assign WCNext = WCA << 2;
@ -94,7 +94,7 @@ module fdivsqrtstage4 (
assign CNext = {2'b11, C[`DIVb+1:2]};
// On-the-fly converter to accumulate result
fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtE), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
endmodule

1
pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
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@ -32,7 +32,6 @@
module fdivsqrtuotfc4(
input logic [3:0] udigit,
input logic Sqrt,
input logic [`DIVb:0] U, UM,
input logic [`DIVb:0] C,
output logic [`DIVb:0] UNext, UMNext