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Changed CPUBusy to Stall in ebu modules.

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This commit is contained in:
Ross Thompson 2022-12-11 15:51:35 -06:00
parent 3ddf509f28
commit c50a2bd8bf
7 changed files with 14 additions and 14 deletions
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4
pipelined/src/cache/cache.sv vendored
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@ -35,7 +35,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
input logic reset,
// cpu side
input logic FlushStage,
input logic CPUBusy,
input logic Stall,
input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic,
input logic FlushCache,
@ -194,7 +194,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Cache FSM
/////////////////////////////////////////////////////////////////////////////////////////////
cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.FlushStage, .CacheRW, .CacheAtomic, .CPUBusy,
.FlushStage, .CacheRW, .CacheAtomic, .Stall,
.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty,

4
pipelined/src/ebu/ahbcacheinterface.sv
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@ -64,7 +64,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
input logic Flush,
input logic [`PA_BITS-1:0] PAdr,
input logic [1:0] BusRW,
input logic CPUBusy,
input logic Stall,
input logic [2:0] Funct3,
output logic SelBusBeat,
output logic BusStall,
@ -114,7 +114,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule

4
pipelined/src/ebu/ahbinterface.sv
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@ -51,7 +51,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
input logic [1:0] BusRW,
input logic [`XLEN/8-1:0] ByteMask,
input logic [`XLEN-1:0] WriteData,
input logic CPUBusy,
input logic Stall,
output logic BusStall,
output logic BusCommitted,
output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer);
@ -73,6 +73,6 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
end
busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE);
endmodule

4
pipelined/src/ebu/buscachefsm.sv
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@ -40,7 +40,7 @@ module buscachefsm #(parameter integer BeatCountThreshold,
// IEU interface
input logic Flush,
input logic [1:0] BusRW,
input logic CPUBusy,
input logic Stall,
output logic BusCommitted,
output logic BusStall,
output logic CaptureEn,
@ -89,7 +89,7 @@ module buscachefsm #(parameter integer BeatCountThreshold,
else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3;
MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;

4
pipelined/src/ebu/busfsm.sv
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@ -38,7 +38,7 @@ module busfsm
// IEU interface
input logic Flush,
input logic [1:0] BusRW,
input logic CPUBusy,
input logic Stall,
output logic BusCommitted,
output logic BusStall,
output logic CaptureEn,
@ -65,7 +65,7 @@ module busfsm
else NextState = ADR_PHASE;
DATA_PHASE: if(HREADY) NextState = MEM3;
else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3;
MEM3: if(Stall) NextState = MEM3;
else NextState = ADR_PHASE;
default: NextState = ADR_PHASE;
endcase

4
pipelined/src/ifu/ifu.sv
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@ -243,7 +243,7 @@ module ifu (
.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
.FetchBuffer, .PAdr(PCPF),
.BusRW, .CPUBusy,
.BusRW, .Stall(CPUBusy),
.BusStall, .BusCommitted(BusCommittedF));
mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
@ -260,7 +260,7 @@ module ifu (
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
.Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
assign CacheCommittedF = '0;
if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);

4
pipelined/src/lsu/lsu.sv
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@ -270,7 +270,7 @@ module lsu (
.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(CPUBusy),
.BusStall, .BusCommitted(BusCommittedM));
// FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times.
@ -293,7 +293,7 @@ module lsu (
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
.Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];