forked from Github_Repos/cvw
Add back SV for integer division to use 8-bit CPA in qslc
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@ -195,7 +195,7 @@ module divide4 #(parameter WIDTH=64)
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logic [WIDTH:0] Qstar;
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logic [WIDTH:0] QMstar;
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logic [WIDTH:0] QM2star;
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logic [6:0] qtotal;
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logic [7:0] qtotal;
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logic [WIDTH+3:0] SumN, CarryN, SumN2, CarryN2;
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logic [WIDTH+3:0] divi1, divi2, divi1c, divi2c, dive1;
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logic [WIDTH+3:0] mdivi_temp, mdivi;
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@ -219,9 +219,9 @@ module divide4 #(parameter WIDTH=64)
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mux2 #(WIDTH+4) mx2 ({CarryN2[WIDTH+1:0], 2'h0}, {WIDTH+4{1'b0}}, state0, CarryN);
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mux2 #(WIDTH+4) mx3 ({SumN2[WIDTH+1:0], 2'h0}, dive1, state0, SumN);
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// Simplify QST
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adder #(7) cpa1 (SumN[WIDTH+3:WIDTH-3], CarryN[WIDTH+3:WIDTH-3], qtotal);
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adder #(8) cpa1 (SumN[WIDTH+3:WIDTH-4], CarryN[WIDTH+3:WIDTH-4], qtotal);
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// q = {+2, +1, -1, -2} else q = 0
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qst4 pd1 (qtotal[6:0], divi1[WIDTH-1:WIDTH-3], quotient);
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qst4 pd1 (qtotal[7:1], divi1[WIDTH-1:WIDTH-3], quotient);
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assign ulp = quotient[2]|quotient[3];
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assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]);
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// Map to binary encoding
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