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Possible fix to the bus cache interaction.

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This commit is contained in:
Ross Thompson 2022-09-27 11:34:33 -05:00
parent dfe6bdd06d
commit afc6934249
2 changed files with 8 additions and 8 deletions
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12
pipelined/src/cache/cachefsm.sv vendored
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@ -193,14 +193,14 @@ module cachefsm
assign FlushAdrCntRst = (CurrState == STATE_READY);
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
// Bus interface controls
// assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss;
// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
// (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
// (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
// (CurrState == STATE_FLUSH_CHECK & VictimDirty);
assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
// assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss;
assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
(CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
// (CurrState == STATE_FLUSH_CHECK & VictimDirty);
// **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want DCacheTrapM in the critical path

4
pipelined/src/ebu/buscachefsm.sv
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@ -140,8 +140,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
// AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) |
(CurrState == DATA_PHASE & ~HREADY) |
(CacheAccess & ~|WordCount & |CacheBusRW) ? AHB_NONSEQ : // if we have a pipelined request
(CurrState == DATA_PHASE & ~HREADY) | // *** this is wrong.
(CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_EVICT & |WordCount);