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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-12-21 14:12:25 -08:00
commit d0a3e939e3
3 changed files with 9 additions and 9 deletions
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2
fpga/constraints/debug2.xdc
View File

@ -316,7 +316,7 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe62]

12
fpga/generator/Makefile
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@ -1,13 +1,13 @@
dst := IP
# vcu118
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export board := vcu118
export XILINX_PART := xcvu9p-flga2104-2L-e
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
all: FPGA

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -127,10 +127,10 @@ module fdivsqrtpostproc(
always_comb
if (RemOpM) begin
NormShiftM = (m + (`DIVBLEN)'(`DIVa));
NormShiftM = (m + (`DIVBLEN+1)'(`DIVa));
PreResultM = IntRemM;
end else begin
NormShiftM = ((`DIVBLEN)'(`DIVb) - (n << `LOGR));
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR));
PreResultM = {3'b000, IntQuotM};
end