forked from Github_Repos/cvw
removed ethe second bit from fma alignment shift
This commit is contained in:
Katherine Parry
parent
3adb8efb2b
commit
aca6f0d4e6
@ -104,9 +104,9 @@
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`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
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`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
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`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
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`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+7) ? (`QLEN+`NF+1) : (3*`NF+7))//change
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`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+6) ? (`QLEN+`NF+1) : (3*`NF+6))
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`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
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`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+7) ? (`DIVRESLEN+`NF) : (3*`NF+5))//change
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`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+6) ? (`DIVRESLEN+`NF) : (3*`NF+4))
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// division constants
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`define RADIX 32'h4
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@ -31,27 +31,37 @@
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`include "wally-config.vh"
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module fma(
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input logic Xs, Ys, Zs, // input's signs
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input logic [`NE-1:0] Xe, Ye, Ze, // input's biased exponents in B(NE.0) format
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input logic [`NF:0] Xm, Ym, Zm, // input's significands in U(0.NF) format
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input logic XZero, YZero, ZZero, // is the input zero
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input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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output logic ASticky, // sticky bit that is calculated during alignment
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output logic [3*`NF+4:0] Sm,//change // the positive sum's significand
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other opperations)
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output logic Ps, // the product's sign
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output logic Ss, // the sum's sign
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output logic [`NE+1:0] Se,
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output logic [$clog2(3*`NF+6)-1:0] SCnt//change // normalization shift count
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input logic Xs, Ys, Zs, // input's signs
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input logic [`NE-1:0] Xe, Ye, Ze, // input's biased exponents in B(NE.0) format
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input logic [`NF:0] Xm, Ym, Zm, // input's significands in U(0.NF) format
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input logic XZero, YZero, ZZero, // is the input zero
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input logic [2:0] OpCtrl, // operation control
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output logic ASticky, // sticky bit that is calculated during alignment
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output logic [3*`NF+3:0] Sm, // the positive sum's significand
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other opperations)
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output logic Ps, // the product's sign
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output logic Ss, // the sum's sign
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output logic [`NE+1:0] Se, // the sum's exponent
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output logic [$clog2(3*`NF+5)-1:0] SCnt // normalization shift count
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);
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logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format
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logic [3*`NF+4:0] Am;//change // addend aligned's mantissa for addition in U(NF+5.2NF+1)
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logic [3*`NF+4:0] AmInv; //change // aligned addend's mantissa possibly inverted
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logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed
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logic KillProd; // set the product to zero before addition if the product is too small to matter
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logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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// OpCtrl:
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// Fma: {not multiply-add?, negate prod?, negate Z?}
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// 000 - fmadd
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// 001 - fmsub
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// 010 - fnmsub
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// 011 - fnmadd
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// 100 - mul
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// 110 - add
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// 111 - sub
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logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format
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logic [3*`NF+3:0] Am; // addend aligned's mantissa for addition in U(NF+4.2NF)
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logic [3*`NF+3:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed U(2.2Nf)
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logic KillProd; // set the product to zero before addition if the product is too small to matter
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logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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///////////////////////////////////////////////////////////////////////////////
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// Calculate the product
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@ -68,25 +78,23 @@ module fma(
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// multiplication of the mantissa's
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fmamult mult(.Xm, .Ym, .Pm);
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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// calculate the signs and take the opperation into account
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fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA);
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye,
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.Am, .ASticky, .KillProd);
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// ///////////////////////////////////////////////////////////////////////////////
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// // Addition/LZA
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// ///////////////////////////////////////////////////////////////////////////////
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fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
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//change
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fmalza #(3*`NF+5) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ASticky&KillProd}), .Cin(InvA & ~(ASticky & ~KillProd)), .sub(InvA), .SCnt);
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fmalza #(3*`NF+4) lza(.A(AmInv), .Pm({PmKilled, InvA&Ps&ASticky&KillProd}), .Cin(InvA & ~(ASticky & ~KillProd)), .sub(InvA), .SCnt);
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endmodule
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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module fmaadd(
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input logic [3*`NF+4:0] Am, //change // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [3*`NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [2*`NF+1:0] Pm, // the product's mantissa
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input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
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input logic InvA, // invert the aligned addend
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@ -39,13 +39,13 @@ module fmaadd(
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input logic ASticky,
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input logic [`NE-1:0] Ze,
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input logic [`NE+1:0] Pe,
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output logic [3*`NF+4:0] AmInv,//change // aligned addend possibly inverted
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output logic [3*`NF+3:0] AmInv, // aligned addend possibly inverted
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output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic Ss,
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output logic [`NE+1:0] Se,
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output logic [3*`NF+4:0] Sm//change // the positive sum
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output logic [3*`NF+3:0] Sm // the positive sum
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);
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logic [3*`NF+4:0] PreSum, NegPreSum;//change // possibly negitive sum
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logic [3*`NF+3:0] PreSum, NegPreSum; // possibly negitive sum
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logic [3*`NF+5:0] PreSumdebug, NegPreSumdebug; // possibly negitive sum
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logic NegSum; // was the sum negitive
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logic NegSumdebug; // was the sum negitive
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@ -66,8 +66,8 @@ module fmaadd(
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// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
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// ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA
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// in this case this result is only ever selected when InvA=1 so we can remove &InvA
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assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+5{1'b0}}, (~ASticky|KillProd)&InvA};//change
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assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+2)'(0), ~ASticky|~KillProd, 2'b0};//change
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assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*`NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
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assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*`NF+2)'(0), ~ASticky|~KillProd, 1'b0};
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum : PreSum;
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@ -35,16 +35,15 @@ module fmaalign(
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input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [`NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*`NF+4:0] Am,//change // addend aligned for addition in U(NF+5.2NF+1)
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output logic [3*`NF+3:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ASticky, // Sticky bit calculated from the aliged addend
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output logic KillProd // should the product be set to zero
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);
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logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
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logic [4*`NF+4:0] ZmShifted;//change // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*`NF+4:0] ZmPreshifted;//change // input to the alignment shifter U(NF+5.3NF+1)
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logic [4*`NF+3:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*`NF+3:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic KillZ;
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logic PmSticky, tmpZmSticky;
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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@ -57,38 +56,38 @@ module fmaalign(
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+2) - {2'b0, Ze};
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// Defualt Addition with only inital left shift
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// | 53'b0 | 106'b(product) | 2'b0 |
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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assign ZmPreshifted = {Zm,(3*`NF+4)'(0)}; //change
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assign ZmPreshifted = {Zm,(3*`NF+3)'(0)};
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assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
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assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(4));//change
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assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(3));
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always_comb
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begin
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// If the product is too small to effect the sum, kill the product
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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if (KillProd) begin
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ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+2)'(0)};//change
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ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+1)'(0)};
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ASticky = ~(XZero|YZero);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the product to be considered too small
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// - The 2 extra bits are needed for rounding
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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end else if (KillZ) begin
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ZmShifted = 0;
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ASticky = ~ZZero;
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// If the Addend is shifted right
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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end else begin
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ZmShifted = ZmPreshifted >> ACnt;
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ASticky = |(ZmShifted[`NF-1:0]);
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@ -96,7 +95,7 @@ module fmaalign(
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end
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end
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assign Am = ZmShifted[4*`NF+4:`NF];//change
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assign Am = ZmShifted[4*`NF+3:`NF];
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endmodule
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@ -31,18 +31,18 @@
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`include "wally-config.vh"
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module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
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input logic [WIDTH-1:0] A, // addend
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input logic [2*`NF+3:0] Pm, // product
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input logic Cin, // carry in
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input logic sub,
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output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result
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input logic [WIDTH-1:0] A, // addend
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input logic [2*`NF+2:0] Pm, // product
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input logic Cin, // carry in
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input logic sub,
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output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result
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);
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logic [WIDTH:0] F;
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logic [WIDTH-1:0] B, P, G, K;
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logic [WIDTH-1:0] Pp1, Gm1, Km1;
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assign B = {{(`NF+1){1'b0}}, Pm};//change // Zero extend product
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assign B = {{(`NF+1){1'b0}}, Pm}; // Zero extend product
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assign P = A^B;
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assign G = A&B;
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@ -109,14 +109,14 @@ module fpu (
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logic XExpMaxE; // is the exponent all ones (max value)
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// Fma Signals
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logic [3*`NF+4:0] SmE, SmM;//change
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logic ZmStickyE, ZmStickyM;
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logic [3*`NF+3:0] SmE, SmM;
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logic FmaAStickyE, FmaAStickyM;
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logic [`NE+1:0] SeE,SeM;
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logic InvAE, InvAM;
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logic AsE, AsM;
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logic PsE, PsM;
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logic SsE, SsM;
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logic [$clog2(3*`NF+6)-1:0] SCntE, SCntM;//change
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logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;
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// Cvt Signals
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logic [`NE:0] CeE, CeM; // the calculated expoent
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@ -258,7 +258,7 @@ module fpu (
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.As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE),
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.Sm(SmE),
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.InvA(InvAE), .SCnt(SCntE),
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.ASticky(ZmStickyE));
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.ASticky(FmaAStickyE));
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// divide and squareroot
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// - fdiv
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@ -352,10 +352,10 @@ module fpu (
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{XsE, YsE, XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE, ZDenormE},
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{XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM});
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flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
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flopenrc #(3*`NF+5) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);//change
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flopenrc #($clog2(3*`NF+6)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, //change
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{ZmStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
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{ZmStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
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flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
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flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
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{FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
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{FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
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flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
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{CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE},
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{CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM});
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@ -375,7 +375,7 @@ module fpu (
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assign FpLoadStoreM = FResSelM[1];
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postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM),
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.FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
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.ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
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@ -30,18 +30,18 @@
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`include "wally-config.vh"
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module fmashiftcalc(
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input logic [3*`NF+4:0] FmaSm,//change // the positive sum
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input logic [$clog2(3*`NF+6)-1:0] FmaSCnt,//change // normalization shift count
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input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic [`NE+1:0] FmaSe,
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output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
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output logic FmaSZero, // is the result denormalized - calculated before LZA corection
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output logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection
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output logic [$clog2(3*`NF+6)-1:0] FmaShiftAmt,//change // normalization shift count
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output logic [3*`NF+6:0] FmaShiftIn//change // is the sum zero
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input logic [3*`NF+3:0] FmaSm, // the positive sum
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input logic [$clog2(3*`NF+5)-1:0] FmaSCnt, // normalization shift count
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input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic [`NE+1:0] FmaSe, // sum's exponent
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output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
|
||||
output logic FmaSZero, // is the result denormalized - calculated before LZA corection
|
||||
output logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection
|
||||
output logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt, // normalization shift count
|
||||
output logic [3*`NF+5:0] FmaShiftIn // is the sum zero
|
||||
);
|
||||
logic [`NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the `FLEN bias
|
||||
logic [`NE+1:0] BiasCorr;
|
||||
logic [`NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the `FLEN bias
|
||||
logic [`NE+1:0] BiasCorr; // correction for bias
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Normalization
|
||||
@ -50,7 +50,7 @@ module fmashiftcalc(
|
||||
// Determine if the sum is zero
|
||||
assign FmaSZero = ~(|FmaSm);
|
||||
// calculate the sum's exponent
|
||||
assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+6)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);//change
|
||||
assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+5)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);
|
||||
|
||||
//convert the sum's exponent into the proper percision
|
||||
if (`FPSIZES == 1) begin
|
||||
@ -150,7 +150,7 @@ module fmashiftcalc(
|
||||
// - shift once if killing a product and the result is denormalized
|
||||
assign FmaShiftIn = {2'b0, FmaSm};
|
||||
if (`FPSIZES == 1)
|
||||
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+6)-1:0]+($clog2(3*`NF+6))'(`NF+2): FmaSCnt+1;//change
|
||||
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;
|
||||
else
|
||||
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+6)-1:0]+($clog2(3*`NF+6))'(`NF+2)+BiasCorr[$clog2(3*`NF+6)-1:0]: FmaSCnt+1;//change
|
||||
assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2)+BiasCorr[$clog2(3*`NF+5)-1:0]: FmaSCnt+1;
|
||||
endmodule
|
||||
|
||||
@ -32,28 +32,27 @@
|
||||
|
||||
module postprocess (
|
||||
// general signals
|
||||
input logic Xs, Ys, // input signs
|
||||
input logic Xs, Ys, // input signs
|
||||
input logic [`NF:0] Xm, Ym, Zm, // input mantissas
|
||||
input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
|
||||
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
|
||||
input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
|
||||
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
|
||||
input logic XZero, YZero, ZZero, // inputs are zero
|
||||
input logic XInf, YInf, ZInf, // inputs are infinity
|
||||
input logic XNaN, YNaN, ZNaN, // inputs are NaN
|
||||
input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
|
||||
input logic ZDenorm, // is the original precision denormalized
|
||||
input logic [1:0] PostProcSel, // select result to be written to fp register
|
||||
input logic ZDenorm, // is the original precision denormalized
|
||||
input logic [1:0] PostProcSel, // select result to be written to fp register
|
||||
//fma signals
|
||||
input logic FmaAs, // the modified Z sign - depends on instruction
|
||||
input logic FmaPs, // the product's sign
|
||||
input logic [`NE+1:0] FmaSe,
|
||||
input logic [3*`NF+4:0] FmaSm,//change // the positive sum
|
||||
input logic FmaZmS, // sticky bit that is calculated during alignment
|
||||
input logic FmaSs,
|
||||
input logic [$clog2(3*`NF+6)-1:0] FmaSCnt,//change // the normalization shift count
|
||||
input logic FmaAs, // the modified Z sign - depends on instruction
|
||||
input logic FmaPs, // the product's sign
|
||||
input logic [`NE+1:0] FmaSe, // the sum's exponent
|
||||
input logic [3*`NF+3:0] FmaSm, // the positive sum
|
||||
input logic FmaASticky, // sticky bit that is calculated during alignment
|
||||
input logic FmaSs, //
|
||||
input logic [$clog2(3*`NF+5)-1:0] FmaSCnt, // the normalization shift count
|
||||
//divide signals
|
||||
input logic DivS,
|
||||
// input logic DivDone,
|
||||
input logic [`NE+1:0] DivQe,
|
||||
input logic [`DIVb:0] DivQm,
|
||||
// conversion signals
|
||||
@ -89,10 +88,10 @@ module postprocess (
|
||||
// fma signals
|
||||
logic [`NE+1:0] FmaMe; // exponent of the normalized sum
|
||||
logic FmaSZero; // is the sum zero
|
||||
logic [3*`NF+6:0] FmaShiftIn;//change // shift input
|
||||
logic [3*`NF+5:0] FmaShiftIn; // shift input
|
||||
logic [`NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account denormal or zero results
|
||||
logic FmaPreResultDenorm; // is the result denormalized - calculated before LZA corection
|
||||
logic [$clog2(3*`NF+6)-1:0] FmaShiftAmt;//change // normalization shift count
|
||||
logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt; // normalization shift count
|
||||
// division singals
|
||||
logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;
|
||||
logic [`NORMSHIFTSZ-1:0] DivShiftIn;
|
||||
@ -152,8 +151,8 @@ module postprocess (
|
||||
always_comb
|
||||
case(PostProcSel)
|
||||
2'b10: begin // fma
|
||||
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+6){1'b0}}, FmaShiftAmt};//change
|
||||
ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+7){1'b0}}};//change
|
||||
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+5){1'b0}}, FmaShiftAmt};
|
||||
ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+6){1'b0}}};
|
||||
end
|
||||
2'b00: begin // cvt
|
||||
ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
|
||||
@ -193,7 +192,7 @@ module postprocess (
|
||||
|
||||
roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
|
||||
|
||||
round round(.OutFmt, .Frm, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
|
||||
round round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
|
||||
.Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf,
|
||||
.DivS, //.DivDone,
|
||||
.DivOp, .UfPlus1, .FullRe, .Rf, .Re, .S, .R, .G, .Me);
|
||||
|
||||
@ -48,7 +48,7 @@ module round(
|
||||
input logic CvtResDenormUf,
|
||||
input logic CvtResUf,
|
||||
input logic [`CORRSHIFTSZ-1:0] Mf,
|
||||
input logic FmaZmS, // addend's sticky bit
|
||||
input logic FmaASticky, // addend's sticky bit
|
||||
input logic [`NE+1:0] FmaMe, // exponent of the normalized sum
|
||||
input logic Ms, // the result's sign
|
||||
input logic [`NE:0] CvtCe, // the calculated expoent
|
||||
@ -175,7 +175,7 @@ module round(
|
||||
|
||||
// only add the Addend sticky if doing an FMA opperation
|
||||
// - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
|
||||
assign S = FmaZmS&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp;
|
||||
assign S = FmaASticky&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp;
|
||||
|
||||
// determine round and LSB of the rounded value
|
||||
// - underflow round bit is used to determint the underflow flag
|
||||
|
||||
@ -43,7 +43,7 @@ module shiftcorrection(
|
||||
output logic [`NE+1:0] Qe,
|
||||
output logic [`NE+1:0] FmaMe // exponent of the normalized sum
|
||||
);
|
||||
logic [3*`NF+4:0] CorrSumShifted;//change // the shifted sum after LZA correction
|
||||
logic [3*`NF+3:0] CorrSumShifted; // the shifted sum after LZA correction
|
||||
logic [`CORRSHIFTSZ-1:0] CorrQmShifted;
|
||||
logic ResDenorm; // is the result denormalized
|
||||
logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction
|
||||
@ -56,7 +56,7 @@ module shiftcorrection(
|
||||
assign CorrQmShifted = (LZAPlus1|(DivQe==1&~LZAPlus1)) ? Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1] : Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
|
||||
// if the result of the divider was calculated to be denormalized, then the result was correctly normalized, so select the top shifted bits
|
||||
always_comb
|
||||
if(FmaOp) Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+5){1'b0}}};//change
|
||||
if(FmaOp) Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+4){1'b0}}};
|
||||
else if (DivOp&~DivResDenorm) Mf = CorrQmShifted;
|
||||
else Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
|
||||
// Determine sum's exponent
|
||||
|
||||
@ -53,39 +53,39 @@ module testbenchfp;
|
||||
logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
|
||||
|
||||
logic [1:0] FmtVal; // value of the current Fmt
|
||||
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal
|
||||
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
|
||||
logic WriteIntVal; // value of the current WriteInt
|
||||
logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
|
||||
logic [`XLEN-1:0] SrcA; // integer input
|
||||
logic [`FLEN-1:0] Ans; // correct answer from TestFloat
|
||||
logic [`FLEN-1:0] Res; // result from other units
|
||||
logic [4:0] AnsFlg; // correct flags read from testfloat
|
||||
logic [4:0] ResFlg, Flg; // Result flags
|
||||
logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||
logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
||||
logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
||||
logic [`FLEN-1:0] Res; // result from other units
|
||||
logic [4:0] AnsFlg; // correct flags read from testfloat
|
||||
logic [4:0] ResFlg, Flg; // Result flags
|
||||
logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||
logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
||||
logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
||||
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
|
||||
logic AnsNaN, ResNaN, NaNGood;
|
||||
logic Xs, Ys, Zs; // sign of the inputs
|
||||
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
||||
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
||||
logic XNaN, YNaN, ZNaN; // is the input NaN
|
||||
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
||||
logic XDenorm, ZDenorm; // is the input denormalized
|
||||
logic XInf, YInf, ZInf; // is the input infinity
|
||||
logic XZero, YZero, ZZero; // is the input zero
|
||||
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
||||
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
||||
logic IntZero;
|
||||
logic CvtResSgnE;
|
||||
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
||||
logic Xs, Ys, Zs; // sign of the inputs
|
||||
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
||||
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
||||
logic XNaN, YNaN, ZNaN; // is the input NaN
|
||||
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
||||
logic XDenorm, ZDenorm; // is the input denormalized
|
||||
logic XInf, YInf, ZInf; // is the input infinity
|
||||
logic XZero, YZero, ZZero; // is the input zero
|
||||
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
||||
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
||||
logic IntZero;
|
||||
logic CvtResSgnE;
|
||||
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
||||
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
||||
logic [`DIVb:0] Quot;
|
||||
logic CvtResDenormUfE;
|
||||
logic DivStart, FDivBusyE, OldFDivBusyE;
|
||||
logic reset = 1'b0;
|
||||
logic [`DIVb:0] Quot;
|
||||
logic CvtResDenormUfE;
|
||||
logic DivStart, FDivBusyE, OldFDivBusyE;
|
||||
logic reset = 1'b0;
|
||||
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
|
||||
logic [`DURLEN-1:0] Dur;
|
||||
logic [`DURLEN-1:0] Dur;
|
||||
|
||||
// in-between FMA signals
|
||||
logic Mult;
|
||||
@ -94,17 +94,17 @@ module testbenchfp;
|
||||
logic [`NE+1:0] Se;
|
||||
logic ASticky;
|
||||
logic KillProd;
|
||||
logic [$clog2(3*`NF+6)-1:0] SCnt;
|
||||
logic [3*`NF+4:0] Sm;
|
||||
logic [$clog2(3*`NF+5)-1:0] SCnt;
|
||||
logic [3*`NF+3:0] Sm;
|
||||
logic InvA;
|
||||
logic NegSum;
|
||||
logic As;
|
||||
logic Ps;
|
||||
logic DivSticky;
|
||||
logic DivDone;
|
||||
logic DivNegSticky;
|
||||
logic [`NE+1:0] DivCalcExp;
|
||||
logic divsqrtop;
|
||||
logic DivSticky;
|
||||
logic DivDone;
|
||||
logic DivNegSticky;
|
||||
logic [`NE+1:0] DivCalcExp;
|
||||
logic divsqrtop;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
Loading…
Reference in New Issue
Block a user