Formatting progress.

pipelined/src/ebu/ahbcacheinterface.sv

@@ -30,7 +30,7 @@
 
 `include "wally-config.vh"
 
-module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) (
+module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHBW, CACHE_ENABLED) (
   input  logic                 HCLK, HRESETn,
   // bus interface
   input logic                 HREADY,                  // AHB peripheral ready
@@ -47,26 +47,25 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
   input logic [`PA_BITS-1:0]  CacheBusAdr,             // Address of cache line
   input logic [`LLEN-1:0]     CacheReadDataWordM,      // one word of cache line during a writeback
   input logic                 CacheableOrFlushCacheM,  // Memory operation is cacheable or flushing D$
+  input logic                 Cacheable,               // Memory operation is cachable
   input logic [1:0]           CacheBusRW,              // Cache bus operation, 01: writeback, 10: fetch
   output logic                CacheBusAck,             // Handshack to $ indicating bus transaction completed
   output logic [LINELEN-1:0]  FetchBuffer,             // Register to hold beats of cache line as the arrive from bus
   output logic [LOGWPL-1:0]   BeatCount,               // Beat position within the cache line
-  input logic                 Cacheable,               // Memory operation is cachable
+  output logic                SelBusBeat,              // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
 
   // uncached interface 
+  input logic [`PA_BITS-1:0]  PAdr,                    // Physical address of uncached memory operation
   input logic [`LLEN-1:0]     WriteDataM,              // IEU write data for uncached store
+  input logic [1:0]           BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
+  input logic [2:0]           Funct3,                  // Size of uncached memory operation
 
   // lsu/ifu interface
+  input logic                 Stall,                   // Core pipeline is stalled
   input logic                 Flush,                   // Pipeline stage flush. Prevents bus transaction from starting
-  input logic [`PA_BITS-1:0]  PAdr,                    // Physical address of uncached memory operation
-  input logic [1:0]           BusRW,                   // 
-  input logic                 Stall,
-  input logic [2:0]           Funct3,
-  output logic                SelBusBeat,
-  output logic                BusStall,
-  output logic                BusCommitted);
+  output logic                BusStall,                // Bus is busy with an in flight memory operation
+  output logic                BusCommitted);           // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
   
-  localparam integer           LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
 
   localparam integer           BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
   logic [`PA_BITS-1:0]         LocalHADDR;

pipelined/src/ifu/ifu.sv

@@ -201,6 +201,7 @@ module ifu (
     localparam integer   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
     if(`ICACHE) begin : icache
       localparam integer   LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
+      localparam integer   LLENPOVERAHBW = `LLEN / `AHBW;                     // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
       logic [LINELEN-1:0]  FetchBuffer;
       logic [`PA_BITS-1:0] ICacheBusAdr;
       logic                ICacheBusAck;
@@ -226,7 +227,7 @@ module ifu (
              .NextAdr(PCNextFSpill[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
-      ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) 
+      ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, LLENPOVERAHBW, `ICACHE) 
       ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
             .HRDATA,
             .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),

pipelined/src/lsu/lsu.sv

@@ -272,7 +272,7 @@ module lsu (
         .FetchBuffer, .CacheBusRW, 
         .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
 
-      ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
+      ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .LLENPOVERAHBW(LLENPOVERAHBW), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
         .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
         .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
         .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),