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Added necessary files to make bit make and run bit manipulation tests as part of regression

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Kip Macsai-Goren 2023-02-10 10:35:19 -08:00
parent f91d74896a
commit f9d934e5ae
6 changed files with 763 additions and 702 deletions
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8
config/rv64gc/wally-config.vh
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@ -145,10 +145,10 @@
`define DIVCOPIES 32'h4
// bit manipulation
`define ZBA_SUPPORTED 0
`define ZBB_SUPPORTED 0
`define ZBC_SUPPORTED 0
`define ZBS_SUPPORTED 0
`define ZBA_SUPPORTED 1
`define ZBB_SUPPORTED 1
`define ZBC_SUPPORTED 1
`define ZBS_SUPPORTED 1
// Memory synthesis configuration
`define USE_SRAM 0

2
sim/sim-wally-batch
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@ -1 +1 @@
vsim -c -do "do wally-batch.do rv32gc wally32priv"
vsim -c -do "do wally-batch.do rv64gc arch64b"

1
testbench/testbench.sv
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@ -105,6 +105,7 @@ logic [3:0] dummy;
"coremark": tests = coremark;
"fpga": tests = fpga;
"ahb" : tests = ahb;
"arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b;
endcase
end else begin // RV32
case (TEST)

1437
testbench/tests.vh
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File diff suppressed because it is too large Load Diff

13
tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py Normal file
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@ -0,0 +1,13 @@
import os
os.chdir("/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src")
filenames = []
for testname in os.listdir():
print(
f"""cd /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/link.ld -I /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/ -I /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature=/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1;
riscv64-unknown-elf-elf2hex --bit-width 64 --input /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile
extractFunctionRadix.sh /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump
""")

4
tests/riscof/spike/spike_rv64gc_isa.yaml
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@ -1,7 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV64IMAFDCSUZicsr_Zifencei
# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
# ISA: RV64IMAFDCSUZicsr_Zifencei
ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]