Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Removed replay from the config files.

Browse Source
This commit is contained in:
Ross Thompson 2022-07-24 00:34:11 -05:00
parent e12e6c3acd
commit 856ac24686
14 changed files with 24 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
pipelined/config/buildroot/wally-config.vh
View File

@ -130,5 +130,4 @@
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 1

1
pipelined/config/fpga/wally-config.vh
View File

@ -141,5 +141,4 @@
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 1

1
pipelined/config/rv32e/wally-config.vh
View File

@ -135,5 +135,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv32gc/wally-config.vh
View File

@ -133,5 +133,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

2
pipelined/config/rv32i/wally-config.vh
View File

@ -135,6 +135,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

2
pipelined/config/rv32ic/wally-config.vh
View File

@ -133,6 +133,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

2
pipelined/config/rv64BP/wally-config.vh
View File

@ -136,6 +136,4 @@
`define TESTSBP 1
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv64fp/wally-config.vh
View File

@ -137,5 +137,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv64fpquad/wally-config.vh
View File

@ -136,5 +136,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv64gc/wally-config.vh
View File

@ -136,5 +136,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv64i/wally-config.vh
View File

@ -136,5 +136,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

1
pipelined/config/rv64ic/wally-config.vh
View File

@ -136,5 +136,4 @@
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

2
pipelined/regression/wally-pipelined.do
View File

@ -38,7 +38,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7
#-- Run the Simulation
run -all
#run -all
add log -recursive /*
do linux-wave.do
run -all

45
pipelined/src/cache/cachefsm.sv vendored
View File

@ -131,29 +131,31 @@ module cachefsm
always_comb begin
NextState = STATE_READY;
case (CurrState)
STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY;
else if(DoFlush) NextState = STATE_FLUSH;
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // fetch first, then eviction is necessary. see delay in lru read/write path.
else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE;
STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY;
else if(DoFlush) NextState = STATE_FLUSH;
// Delayed LRU update. Cannot check if victim line is dirty on this cycle.
// To optimize do the fetch first, then eviction if necessary.
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV;
else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE;
else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY_START;
else NextState = STATE_MISS_FETCH_WDV;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; // cpu_busy not needed. load misses have the property of reading from the bus buffer rather than sram.
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
else NextState = STATE_MISS_EVICT_DIRTY;
STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if(FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
else NextState = STATE_MISS_FETCH_WDV;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY;
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
else NextState = STATE_MISS_EVICT_DIRTY;
STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if(FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_WRITE_BACK: if(CacheBusAck) begin
if(FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
end else NextState = STATE_FLUSH_WRITE_BACK;
default: NextState = STATE_READY;
if(FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK;
end else NextState = STATE_FLUSH_WRITE_BACK;
default: NextState = STATE_READY;
endcase
end
@ -198,7 +200,6 @@ module cachefsm
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
(CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
(CurrState == STATE_READY & (DoAnyMiss)) |
(CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_EVICT_DIRTY) |