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Renamed signals to E and M stages, forwarded preprocessed n to fsm

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This commit is contained in:
cturek 2022-12-22 00:43:27 +00:00
parent 84f8d9953f
commit c3fdc0ab23
8 changed files with 34 additions and 34 deletions
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14
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -66,29 +66,29 @@ module fdivsqrt(
logic Firstun;
logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE;
logic SpecialCaseM;
logic [`DIVBLEN:0] n, m;
logic OTFCSwap, ALTBM, As;
logic [`DIVBLEN:0] nE, nM, mM;
logic OTFCSwapE, ALTBM, As;
logic DivStartE;
fdivsqrtpreproc fdivsqrtpreproc(
.clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
.Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc,
.n, .m, .OTFCSwap, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
.nE, .nM, .mM, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE,
.clk, .reset, .FmtE, .XsE, .SqrtE, .nE,
.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */
.XZeroE, .YZeroE, .AZeroE, .BZeroE,
.XNaNE, .YNaNE, .MDUE, .n,
.XNaNE, .YNaNE, .MDUE,
.XInfE, .YInfE, .WZeroM, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
.X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
.IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap,
.IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwapE,
.FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE,
.n, .ALTBM, .m, .BZeroM, .As,
.nM, .ALTBM, .mM, .BZeroM, .As,
.QmM, .WZeroM, .DivSM, .FPIntDivResultM);
endmodule

4
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -46,7 +46,7 @@ module fdivsqrtfsm(
input logic FlushE,
input logic WZeroM,
input logic MDUE,
input logic [`DIVBLEN:0] n,
input logic [`DIVBLEN:0] nE,
output logic IFDivStartE,
output logic FDivBusyE, FDivDoneE,
output logic SpecialCaseM
@ -104,7 +104,7 @@ module fdivsqrtfsm(
always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
cycles = MDUE ? nE : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end
/* verilator lint_on WIDTH */

6
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -38,7 +38,7 @@ module fdivsqrtiter(
input logic XZeroE, YZeroE,
input logic SqrtE, MDUE,
// input logic SqrtM,
input logic OTFCSwap,
input logic OTFCSwapE,
input logic [`DIVb+3:0] X,
input logic [`DIVb-1:0] DPreproc,
output logic [`DIVb-1:0] D,
@ -114,13 +114,13 @@ module fdivsqrtiter(
generate
for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
if (`RADIX == 2) begin: stage
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwap, .MDUE,
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE, .OTFCSwapE, .MDUE,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end else begin: stage
logic j1;
assign j1 = (i == 0 & ~C[0][`DIVb-1]);
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwap, .MDUE,
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, .OTFCSwapE, .MDUE,
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end

6
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -40,7 +40,7 @@ module fdivsqrtpostproc(
input logic SpecialCaseM,
input logic [`XLEN-1:0] ForwardedSrcAE,
input logic RemOpM, ALTBM, BZeroM, As,
input logic [`DIVBLEN:0] n, m,
input logic [`DIVBLEN:0] nM, mM,
output logic [`DIVb:0] QmM,
output logic WZeroM,
output logic DivSM,
@ -127,10 +127,10 @@ module fdivsqrtpostproc(
always_comb
if (RemOpM) begin
NormShiftM = (m + (`DIVBLEN+1)'(`DIVa));
NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
PreResultM = IntRemM;
end else begin
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR));
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM << `LOGR));
PreResultM = {3'b000, IntQuotM};
end

26
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -41,8 +41,8 @@ module fdivsqrtpreproc (
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [2:0] Funct3E, Funct3M,
input logic MDUE, W64E,
output logic [`DIVBLEN:0] n, m,
output logic OTFCSwap, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
output logic [`DIVBLEN:0] nE, nM, mM,
output logic OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
output logic [`NE+1:0] QeM,
output logic [`DIVb+3:0] X,
output logic [`DIVb-1:0] DPreproc
@ -55,9 +55,9 @@ module fdivsqrtpreproc (
// Intdiv signals
logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
logic [`XLEN-1:0] PosA, PosB;
logic Bs, CalcOTFCSwap, ALTBE;
logic Bs, CalcOTFCSwapE, ALTBE;
logic [`XLEN-1:0] A64, B64;
logic [`DIVBLEN:0] Calcn, Calcm;
logic [`DIVBLEN:0] mE;
logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
logic [`LOGRK-1:0] pPrTrunc;
@ -72,7 +72,7 @@ module fdivsqrtpreproc (
assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
assign CalcOTFCSwap = (As ^ Bs) & MDUE;
assign CalcOTFCSwapE = (As ^ Bs) & MDUE;
assign PosA = As ? -A64 : A64;
assign PosB = Bs ? -B64 : B64;
@ -82,19 +82,19 @@ module fdivsqrtpreproc (
assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
lzc #(`DIVb) lzcX (IFNormLenX, ell);
lzc #(`DIVb) lzcY (IFNormLenD, Calcm);
lzc #(`DIVb) lzcY (IFNormLenD, mE);
assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // had issue with (`DIVBLEN+1)'(~MDUE) so using this instead
assign DPreproc = IFNormLenD << (Calcm + {{`DIVBLEN{1'b0}}, 1'b1}); // replaced ~MDUE with 1 bc we always want that extra left shift
assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); // replaced ~MDUE with 1 bc we always want that extra left shift
assign ZeroDiff = Calcm - ell;
assign ZeroDiff = mE - ell;
assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
assign p = ALTBE ? '0 : ZeroDiff;
assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
assign pPrTrunc = pPlusr[`LOGRK-1:0];
assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
assign Calcn = (pPrCeil << `LOGK) - 1;
assign nE = (pPrCeil << `LOGK) - 1;
assign IntBits = (`DIVBLEN)'(`RK) + p;
assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
@ -119,14 +119,14 @@ module fdivsqrtpreproc (
// DIVRESLEN/(r*`DIVCOPIES)
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
flopen #(1) swapreg(clk, IFDivStartE, CalcOTFCSwap, OTFCSwap);
flopen #(1) swapreg(clk, IFDivStartE, CalcOTFCSwapE, OTFCSwapE); // Retain value for each iteration of divider in Execute stage
flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, Calcn, n);
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, Calcm, m);
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
//flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM); //HERE
expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZeroE, .ell, .m(Calcm), .Qe(QeE));
expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZeroE, .ell, .m(mE), .Qe(QeE));
endmodule

4
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
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@ -34,7 +34,7 @@ module fdivsqrtqsel4cmp (
input logic [2:0] Dmsbs,
input logic [4:0] Smsbs,
input logic [7:0] WSmsbs, WCmsbs,
input logic SqrtE, j1, OTFCSwap, MDUE,
input logic SqrtE, j1, OTFCSwapE, MDUE,
output logic [3:0] udigit
);
logic [6:0] Wmsbs;
@ -93,5 +93,5 @@ module fdivsqrtqsel4cmp (
else udigitsel = 4'b0001; // choose -2
assign udigitswap = {udigitsel[0], udigitsel[1], udigitsel[2], udigitsel[3]};
assign udigit = OTFCSwap ? udigitswap : udigitsel;
assign udigit = OTFCSwapE ? udigitswap : udigitsel;
endmodule

4
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -38,7 +38,7 @@ module fdivsqrtstage2 (
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE,
input logic OTFCSwap, MDUE,
input logic OTFCSwapE, MDUE,
output logic un,
output logic [`DIVb+1:0] CNext,
output logic [`DIVb:0] UNext, UMNext,
@ -60,7 +60,7 @@ module fdivsqrtstage2 (
// 0000 = 0
// 0010 = -1
// 0001 = -2
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], OTFCSwap, up, uz, un);
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], OTFCSwapE, up, uz, un);
// Sqrt F generation
fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F);

4
pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -36,7 +36,7 @@ module fdivsqrtstage4 (
input logic [`DIVb:0] U, UM,
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE, j1, OTFCSwap, MDUE,
input logic SqrtE, j1, OTFCSwapE, MDUE,
output logic [`DIVb+1:0] CNext,
output logic un,
output logic [`DIVb:0] UNext, UMNext,
@ -65,7 +65,7 @@ module fdivsqrtstage4 (
assign WCmsbs = WC[`DIVb+3:`DIVb-4];
assign WSmsbs = WS[`DIVb+3:`DIVb-4];
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwap, .MDUE);
fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwapE, .MDUE);
assign un = 1'b0; // unused for radix 4
// F generation logic