forked from Github_Repos/cvw
Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now.
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b298a8afc5
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@ -48,8 +48,8 @@ module gshare #(parameter k = 10) (
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logic [k-1:0] GHRNext;
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logic PCSrcM;
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assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
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assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallM & ~FlushM),
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@ -31,16 +31,16 @@
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module gshare_copy #(parameter k = 10) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM,
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input logic FlushD, FlushE, FlushM,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCE,
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input logic [`XLEN-1:0] PCNextF, PCM,
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input logic BranchInstrE, BranchInstrM, PCSrcE
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);
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logic [k-1:0] IndexNextF, IndexE;
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logic [k-1:0] IndexNextF, IndexM;
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logic [1:0] DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionE, NewDirPredictionM;
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@ -48,16 +48,16 @@ module gshare_copy #(parameter k = 10) (
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logic [k-1:0] GHRNext;
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logic PCSrcM;
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assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
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assign IndexNextF = GHRNext ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexM = GHR ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallM & ~FlushM),
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.ra1(IndexNextF),
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.rd1(DirPredictionF),
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.wa2(IndexE),
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.wd2(NewDirPredictionE),
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.we2(BranchInstrE & ~StallM & ~FlushM),
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.wa2(IndexM),
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.wd2(NewDirPredictionM),
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.we2(BranchInstrM & ~StallW & ~FlushW),
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.bwe2(1'b1));
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
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@ -72,9 +72,11 @@ module gshare_copy #(parameter k = 10) (
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flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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/* -----\/----- EXCLUDED -----\/-----
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flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
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flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
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flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
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-----/\----- EXCLUDED -----/\----- */
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endmodule
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