Modified LSU to support DTIM without CSRs.

2022-10-11 14:05:20 -05:00 · 2022-10-11 14:05:20 -05:00 · b2f71b8255
commit b2f71b8255
parent a5c15fd801
1 changed files with 2 additions and 1 deletions
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@ -192,7 +192,8 @@ module lsu (
    assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
    assign PAdrM = IHAdrM[`PA_BITS-1:0];
    assign CacheableM = '1;
-    assign SelDTIM = '0; // if no pma then always select the bus or cache.
+    assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no pma then select dtim if there is a DTIM.  If there is 
+    // a bus then this is always 0. Cannot have both without PMA.
  end
  
  /////////////////////////////////////////////////////////////////////////////////////////////