forked from Github_Repos/cvw
Added performance new counter prints to testbench.
This commit is contained in:
Ross Thompson
parent
17adba5fd5
commit
f6e97cf516
@ -155,9 +155,9 @@ logic [3:0] dummy;
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logic HREADY;
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logic HSELEXT;
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logic InitializingMemories;
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integer ResetCount, ResetThreshold;
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logic InReset;
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logic InitializingMemories;
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integer ResetCount, ResetThreshold;
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logic InReset;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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@ -228,7 +228,7 @@ logic [3:0] dummy;
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// read test vectors into memory
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pathname = tvpaths[tests[0].atoi()];
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/* if (tests[0] == `IMPERASTEST)
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pathname = tvpaths[0];
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pathname = tvpaths[0];
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else pathname = tvpaths[1]; */
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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@ -268,9 +268,6 @@ logic [3:0] dummy;
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// if ($time % 100000 == 0) $display("Time is %0t", $time);
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end
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logic [`XLEN-1:0] debugmemoryadr;
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// assign debugmemoryadr = dut.uncore.uncore.ram.ram.memory.RAM[5140];
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// check results
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assign reset_ext = InReset;
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@ -285,97 +282,97 @@ logic [3:0] dummy;
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ResetCount = 0;
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end
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end else begin
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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// Termination condition (i.e. we finished running current test)
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if (DCacheFlushDone) begin
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integer begin_signature_addr;
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InReset = 1;
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
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testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
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#600; // give time for instructions in pipeline to finish
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
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// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile);
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i = 0;
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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end
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$fclose(outputFilePointer);
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$display("Embench Benchmark: created output file: %s", outputfile);
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, tests[test], ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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// Termination condition (i.e. we finished running current test)
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if (DCacheFlushDone) begin
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integer begin_signature_addr;
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InReset = 1;
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
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testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
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#600; // give time for instructions in pipeline to finish
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
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// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile);
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i = 0;
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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end
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$fclose(outputFilePointer);
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$display("Embench Benchmark: created output file: %s", outputfile);
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, tests[test], ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end
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end
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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logic [`XLEN-1:0] sig;
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop;//***debug
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end
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i = i + 1;
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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logic [`XLEN-1:0] sig;
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop;//***debug
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", tests[test]);
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end
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", tests[test]);
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// move onto the next test, check to see if we're done
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test = test + 1;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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end
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// move onto the next test, check to see if we're done
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test = test + 1;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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InitializingMemories = 1;
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// If there are still additional tests to run, read in information for the next test
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//pathname = tvpaths[tests[0]];
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@ -394,12 +391,12 @@ logic [3:0] dummy;
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
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if(!`FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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if(!`FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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end
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end
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end
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end // if (DCacheFlushDone)
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end // if (DCacheFlushDone)
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end
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end // always @ (negedge clk)
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@ -409,19 +406,29 @@ logic [3:0] dummy;
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string HPMCnames[] = '{"Mcycle",
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"------",
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"InstRet",
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"Load Stall",
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"Br Dir Wrong",
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"Br Count",
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"Br Target Wrong",
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"Jump, JR, Jal",
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"Return",
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"Br Dir Wrong",
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"Br Pred Wrong",
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"Br Target Wrong",
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"RAS Wrong",
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"ret",
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"Instr Class Wrong",
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"Load Stall",
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"Store Stall",
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"D Cache Access",
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"D Cache Miss",
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"D Cache Cycles",
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"I Cache Access",
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"I Cache Miss",
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"Br Pred Wrong"};
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"I Cache Cycles",
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"CSR Write",
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"FenceI",
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"SFenceVMA",
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"Interrupt",
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"Exception",
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"Divide Cycles"
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};
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always @(negedge clk) begin
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if(DCacheFlushStart & ~DCacheFlushDone) begin
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for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
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@ -487,40 +494,22 @@ logic [3:0] dummy;
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if (`BPRED_SUPPORTED == 1) begin
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/* -----\/----- EXCLUDED -----\/-----
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genvar adrindex;
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// Initializing all zeroes into the branch predictor memory.
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for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
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initial begin
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force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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#1;
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release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
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end
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end
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for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
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initial begin
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force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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#1;
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release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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if (`BPRED_LOGGER) begin
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string direction;
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int file;
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logic PCSrcM;
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
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initial
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file = $fopen("branch.log", "w");
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always @(posedge clk) begin
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if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(file, "%h %s\n", dut.core.PCM, direction);
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end
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end
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end
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if (`BPRED_LOGGER) begin
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string direction;
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int file;
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logic PCSrcM;
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
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initial begin
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file = $fopen("branch.log", "w");
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end
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always @(posedge clk) begin
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if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(file, "%h %s\n", dut.core.PCM, direction);
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end
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end
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end
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end
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// check for hange up.
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logic [`XLEN-1:0] OldPCW;
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