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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM

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This commit is contained in:
David Harris 2022-08-25 04:06:27 -07:00
parent fe3147806d
commit a3828420c0
3 changed files with 16 additions and 28 deletions
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12
pipelined/src/ifu/ifu.sv
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@ -185,12 +185,12 @@ module ifu (
assign InstrRawF = AllInstrRawF[31:0];
if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .WriteDataM(), .ByteMaskM('0),
.ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0),
.ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}));
assign {BusStall, IFUBusRead} = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
end
if (`IBUS) begin : bus
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;

19
pipelined/src/lsu/dtim.sv
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@ -31,23 +31,13 @@
module dtim(
input logic clk, reset,
input logic CPUBusy,
input logic [1:0] LSURWM,
input logic [`XLEN-1:0] IEUAdrM,
input logic [`XLEN-1:0] IEUAdrE,
input logic TrapM,
input logic [`LLEN-1:0] WriteDataM,
input logic [`LLEN/8-1:0] ByteMaskM,
input logic Cacheable,
output logic [`LLEN-1:0] ReadDataWordM,
output logic BusStall,
output logic LSUBusWrite,
output logic LSUBusRead,
output logic BusCommittedM,
output logic DCacheStallM,
output logic DCacheCommittedM,
output logic DCacheMiss,
output logic DCacheAccess
output logic [`LLEN-1:0] ReadDataWordM
);
logic we;
@ -60,12 +50,5 @@ module dtim(
bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
assign {DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
endmodule

13
pipelined/src/lsu/lsu.sv
View File

@ -200,10 +200,15 @@ module lsu (
// use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
if (`DMEM) begin : dtim
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
.DCacheStallM, .DCacheCommittedM, .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM),
.DCacheMiss, .DCacheAccess);
dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData - is this done already?
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.
// *** this will have to change to support TIM and bus (DH 8/25/22)
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
assign {DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
end
if (`DBUS) begin : bus
localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;