forked from Github_Repos/cvw
some prostprocessing cleanup
This commit is contained in:
Katherine Parry
parent
67fd3be9d4
commit
575b73fa8c
@ -4,7 +4,7 @@ module flags(
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input logic XSgnM,
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input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
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input logic XInfM, YInfM, ZInfM, // inputs are infinity
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input logic Plus1,
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input logic Plus1,
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input logic InfIn, // is a Inf input being used
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input logic XZeroM, YZeroM, // inputs are zero
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input logic XNaNM, YNaNM, // inputs are NaN
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@ -25,7 +25,7 @@ module flags(
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input logic ZSgnEffM, PSgnM, // the product and modified Z signs
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input logic Round, UfLSBRes, Sticky, UfPlus1, // bits used to determine rounding
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output logic DivByZero,
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output logic IntInvalid, Invalid, Overflow, Underflow, // flags used to select the res
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output logic IntInvalid, Invalid, Overflow, // flags used to select the res
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output logic [4:0] PostProcFlgM // flags
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);
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logic SigNaN; // is an input a signaling NaN
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@ -34,6 +34,7 @@ module flags(
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logic IntInexact; // integer inexact flag
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logic FmaInvalid; // integer invalid flag
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logic DivInvalid; // integer invalid flag
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logic Underflow; // Underflow flag
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logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
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logic ShiftGtIntSz; // is the shift greater than the the integer size (use ResExp to account for possible roundning "shift")
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@ -1,24 +1,24 @@
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`include "wally-config.vh"
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module lzacorrection(
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input logic [`NORMSHIFTSZ-1:0] Shifted, // the shifted sum before LZA correction
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input logic FmaOp,
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input logic DivOp,
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input logic DivResDenorm,
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input logic [`NE+1:0] DivCalcExpM,
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input logic [`NE+1:0] DivDenormShift,
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input logic [`NE+1:0] ConvNormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
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input logic PreResultDenorm, // is the result denormalized - calculated before LZA corection
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input logic KillProdM, // is the product set to zero
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input logic SumZero,
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output logic [`CORRSHIFTSZ-1:0] CorrShifted, // the shifted sum before LZA correction
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output logic [`NE+1:0] CorrDivExp,
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output logic [`NE+1:0] SumExp // exponent of the normalized sum
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input logic [`NORMSHIFTSZ-1:0] Shifted, // the shifted sum before LZA correction
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input logic FmaOp,
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input logic DivOp,
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input logic DivResDenorm,
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input logic [`NE+1:0] DivCalcExpM,
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input logic [`NE+1:0] DivDenormShift,
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input logic [`NE+1:0] ConvNormSumExp, // exponent of the normalized sum not taking into account denormal or zero results
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input logic PreResultDenorm, // is the result denormalized - calculated before LZA corection
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input logic KillProdM, // is the product set to zero
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input logic SumZero,
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output logic [`CORRSHIFTSZ-1:0] CorrShifted, // the shifted sum before LZA correction
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output logic [`NE+1:0] CorrDivExp,
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output logic [`NE+1:0] SumExp // exponent of the normalized sum
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);
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logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
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logic [`CORRSHIFTSZ:0] CorrQuotShifted;
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logic ResDenorm; // is the result denormalized
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logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction
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logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
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logic [`CORRSHIFTSZ:0] CorrQuotShifted;
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logic ResDenorm; // is the result denormalized
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logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction
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// LZA correction
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assign LZAPlus1 = Shifted[`NORMSHIFTSZ-2];
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@ -30,101 +30,109 @@
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`include "wally-config.vh"
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module postprocess(
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// general signals
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input logic XSgnM, YSgnM, // input signs
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input logic [`NE-1:0] ZExpM, // input exponents
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input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
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input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
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input logic AddendStickyM, // sticky bit that is calculated during alignment
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input logic KillProdM, // set the product to zero before addition if the product is too small to matter
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input logic [`NE-1:0] ZExpM, // input exponents
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input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
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input logic [2:0] FOpCtrlM, // choose which opperation (look below for values)
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input logic XZeroM, YZeroM, ZZeroM, // inputs are zero
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input logic XInfM, YInfM, ZInfM, // inputs are infinity
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input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
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input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
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input logic [3*`NF+5:0] SumM, // the positive sum
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input logic ZDenormM, // is the original precision denormalized
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input logic [1:0] PostProcSelM, // select result to be written to fp register
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//fma signals
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input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
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input logic AddendStickyM, // sticky bit that is calculated during alignment
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input logic KillProdM, // set the product to zero before addition if the product is too small to matter
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input logic [3*`NF+5:0] SumM, // the positive sum
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input logic NegSumM, // was the sum negitive
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input logic InvZM, // do you invert Z
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input logic ZDenormM, // is the original precision denormalized
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input logic ZSgnEffM, // the modified Z sign - depends on instruction
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input logic PSgnM, // the product's sign
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input logic [2:0] FOpCtrlM, // choose which opperation (look below for values)
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input logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2M,
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input logic [$clog2(3*`NF+7)-1:0] FmaNormCntM, // the normalization shift count
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic [`NE+1:0] DivCalcExpM, // the calculated expoent
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input logic CvtResDenormUfM,
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input logic DivStickyM,
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input logic DivNegStickyM,
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input logic [`LOGCVTLEN-1:0] CvtShiftAmtM, // how much to shift by
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input logic CvtResSgnM, // the result's sign
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input logic FWriteIntM, // is fp->int (since it's writting to the integer register)
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input logic [`CVTLEN-1:0] CvtLzcInM, // input to the Leading Zero Counter (priority encoder)
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input logic IntZeroM, // is the input zero
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input logic [1:0] PostProcSelM, // select result to be written to fp register
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input logic [`DIVLEN+2:0] Quot,
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output logic [`FLEN-1:0] PostProcResM, // FMA final result
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output logic [4:0] PostProcFlgM,
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output logic [`XLEN-1:0] FCvtIntResM // the int conversion result
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input logic [$clog2(3*`NF+7)-1:0] FmaNormCntM, // the normalization shift count
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//divide signals
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input logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2M,
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input logic [`NE+1:0] DivCalcExpM, // the calculated expoent
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input logic DivStickyM,
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input logic DivNegStickyM,
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input logic [`DIVLEN+2:0] Quot,
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// conversion signals
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic CvtResDenormUfM,
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input logic [`LOGCVTLEN-1:0] CvtShiftAmtM, // how much to shift by
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input logic CvtResSgnM, // the result's sign
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input logic FWriteIntM, // is fp->int (since it's writting to the integer register)
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input logic [`CVTLEN-1:0] CvtLzcInM, // input to the Leading Zero Counter (priority encoder)
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input logic IntZeroM, // is the input zero
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// final results
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output logic [`FLEN-1:0] PostProcResM, // FMA final result
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output logic [4:0] PostProcFlgM,
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output logic [`XLEN-1:0] FCvtIntResM // the int conversion result
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);
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logic [`NF-1:0] ResFrac; // Result fraction
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logic [`NE-1:0] ResExp; // Result exponent
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logic [`CORRSHIFTSZ-1:0] CorrShifted; // the shifted sum before LZA correction
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logic [`NE+1:0] SumExp; // exponent of the normalized sum
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logic [`NE+1:0] FullResExp; // ResExp with bits to determine sign and overflow
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logic SumZero; // is the sum zero
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logic Sticky; // Sticky bit
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logic [3*`NF+8:0] FmaShiftIn; // is the sum zero
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logic UfPlus1; // do you add one (for determining underflow flag)
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logic Round; // bits needed to determine rounding
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logic [`CVTLEN+`NF:0] CvtShiftIn; // number to be shifted
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logic Mult; // multiply opperation
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logic [`FLEN:0] RoundAdd; // how much to add to the result
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logic [`NE+1:0] ConvNormSumExp; // exponent of the normalized sum not taking into account denormal or zero results
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logic PreResultDenorm; // is the result denormalized - calculated before LZA corection
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logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count
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logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count
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logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt;
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logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero
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logic [`NORMSHIFTSZ-1:0] DivShiftIn;
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logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result
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logic Plus1; // add one to the final result?
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logic IntInvalid, Overflow, Underflow, Invalid; // flags
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logic Signed; // is the opperation with a signed integer?
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logic Int64; // is the integer 64 bits?
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logic IntToFp; // is the opperation an int->fp conversion?
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logic ToInt; // is the opperation an fp->int conversion?
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// general signals
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logic [`NF-1:0] ResFrac; // Result fraction
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logic [`NE-1:0] ResExp; // Result exponent
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logic [`CORRSHIFTSZ-1:0] CorrShifted; // corectly shifted fraction
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logic [`NE+1:0] FullResExp; // ResExp with bits to determine sign and overflow
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logic Sticky; // Sticky bit
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logic UfPlus1; // do you add one (for determining underflow flag)
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logic Round; // bits needed to determine rounding
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logic [`FLEN:0] RoundAdd; // how much to add to the result
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logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count
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logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero
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logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result
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logic Plus1; // add one to the final result?
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logic IntInvalid, Overflow, Invalid; // flags
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logic [`NE+1:0] RoundExp;
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logic [`NE+1:0] CorrDivExp;
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logic [1:0] NegResMSBS;
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logic CvtOp;
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logic FmaOp;
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logic CvtResUf;
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logic DivOp;
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logic InfIn;
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logic ResSgn;
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logic RoundSgn;
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logic NaNIn;
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logic DivByZero;
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logic UfLSBRes;
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logic Sqrt;
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logic [`FMTBITS-1:0] OutFmt;
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// fma signals
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logic [`NE+1:0] SumExp; // exponent of the normalized sum
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logic SumZero; // is the sum zero
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logic [3*`NF+8:0] FmaShiftIn; // is the sum zero
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logic [`NE+1:0] ConvNormSumExp; // exponent of the normalized sum not taking into account denormal or zero results
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logic PreResultDenorm; // is the result denormalized - calculated before LZA corection
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logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count
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// division singals
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logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt;
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logic [`NORMSHIFTSZ-1:0] DivShiftIn;
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logic [`NE+1:0] CorrDivExp;
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logic DivByZero;
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logic DivResDenorm;
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logic [`NE+1:0] DivDenormShift;
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// conversion signals
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logic [`CVTLEN+`NF:0] CvtShiftIn; // number to be shifted
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logic [1:0] NegResMSBS;
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logic CvtResUf;
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// readability signals
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logic Mult; // multiply opperation
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logic Int64; // is the integer 64 bits?
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logic Signed; // is the opperation with a signed integer?
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logic IntToFp; // is the opperation an int->fp conversion?
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logic ToInt; // is the opperation an fp->int conversion?
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logic CvtOp;
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logic FmaOp;
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logic DivOp;
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logic InfIn;
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logic NaNIn;
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logic Sqrt;
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// signals to help readability
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assign Signed = FOpCtrlM[0];
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assign Int64 = FOpCtrlM[1];
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assign IntToFp = FOpCtrlM[2];
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assign ToInt = FWriteIntM;
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assign Signed = FOpCtrlM[0];
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assign Int64 = FOpCtrlM[1];
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assign IntToFp = FOpCtrlM[2];
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assign ToInt = FWriteIntM;
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assign Mult = FOpCtrlM[2]&~FOpCtrlM[1]&~FOpCtrlM[0];
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assign CvtOp = (PostProcSelM == 2'b00);
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assign FmaOp = (PostProcSelM == 2'b10);
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assign DivOp = (PostProcSelM == 2'b01);
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assign Sqrt = FOpCtrlM[0];
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assign Sqrt = FOpCtrlM[0];
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// is there an input of infinity or NaN being used
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assign InfIn = (XInfM&~(IntToFp&CvtOp))|(YInfM&~CvtOp)|(ZInfM&FmaOp);
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@ -205,7 +213,7 @@ module postprocess(
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.XSgnM, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCalcExpM,
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.XNaNM, .YNaNM, .NaNIn, .ZSgnEffM, .PSgnM, .Round, .IntInvalid, .DivByZero,
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.UfLSBRes, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullResExp, .Plus1,
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.RoundExp, .NegResMSBS, .Invalid, .Overflow, .Underflow, .PostProcFlgM);
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.RoundExp, .NegResMSBS, .Invalid, .Overflow, .PostProcFlgM);
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///////////////////////////////////////////////////////////////////////////////
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// Select the result
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@ -4,29 +4,27 @@ module resultselect(
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input logic XSgnM, // input signs
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input logic [`NE-1:0] ZExpM, // input exponents
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input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
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input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [`FMTBITS-1:0] OutFmt, // output format
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input logic InfIn,
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input logic XInfM,
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input logic YInfM,
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input logic DivOp,
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input logic XZeroM,
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input logic XInfM, YInfM,
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input logic XZeroM, ZZeroM,
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input logic IntZeroM,
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input logic NaNIn,
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input logic IntToFp,
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input logic Int64,
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input logic Signed,
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input logic CvtOp,
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input logic [`NORMSHIFTSZ-1:0] Shifted, // is the sum zero
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input logic DivOp,
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input logic FmaOp,
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input logic [`NORMSHIFTSZ-1:0] Shifted, // is the sum zero
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input logic Plus1,
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input logic DivByZero,
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic AddendStickyM, // sticky bit that is calculated during alignment
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input logic KillProdM, // set the product to zero before addition if the product is too small to matter
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input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
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input logic ZDenormM, // is the original precision denormalized
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input logic ZZeroM,
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input logic ResSgn, // the res's sign
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input logic [`FLEN:0] RoundAdd, // how much to add to the res
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input logic IntInvalid, Invalid, Overflow, // flags
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@ -8,42 +8,42 @@
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`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
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module round(
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input logic [`FMTBITS-1:0] OutFmt, // precision 1 = double 0 = single
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input logic [2:0] FrmM, // rounding mode
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input logic FmaOp,
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input logic DivOp,
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input logic [1:0] PostProcSelM,
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input logic CvtResDenormUfM,
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input logic ToInt,
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input logic CvtOp,
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input logic CvtResUf,
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input logic [`CORRSHIFTSZ-1:0] CorrShifted,
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input logic AddendStickyM, // addend's sticky bit
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input logic ZZeroM, // is Z zero
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input logic InvZM, // invert Z
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input logic [`NE+1:0] SumExp, // exponent of the normalized sum
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input logic RoundSgn, // the result's sign
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic [`NE+1:0] CorrDivExp, // the calculated expoent
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input logic DivStickyM, // sticky bit
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input logic DivNegStickyM,
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output logic UfPlus1, // do you add or subtract on from the result
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output logic [`NE+1:0] FullResExp, // ResExp with bits to determine sign and overflow
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output logic [`NF-1:0] ResFrac, // Result fraction
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output logic [`NE-1:0] ResExp, // Result exponent
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output logic Sticky, // sticky bit
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output logic [`NE+1:0] RoundExp,
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output logic Plus1,
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output logic [`FLEN:0] RoundAdd, // how much to add to the result
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output logic Round, UfLSBRes // bits needed to calculate rounding
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input logic [`FMTBITS-1:0] OutFmt, // precision 1 = double 0 = single
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input logic [2:0] FrmM, // rounding mode
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input logic FmaOp,
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input logic DivOp,
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input logic CvtOp,
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input logic ToInt,
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input logic [1:0] PostProcSelM,
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input logic CvtResDenormUfM,
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input logic CvtResUf,
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input logic [`CORRSHIFTSZ-1:0] CorrShifted,
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input logic AddendStickyM, // addend's sticky bit
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input logic ZZeroM, // is Z zero
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input logic InvZM, // invert Z
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input logic [`NE+1:0] SumExp, // exponent of the normalized sum
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input logic RoundSgn, // the result's sign
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic [`NE+1:0] CorrDivExp, // the calculated expoent
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input logic DivStickyM, // sticky bit
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input logic DivNegStickyM,
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output logic UfPlus1, // do you add or subtract on from the result
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output logic [`NE+1:0] FullResExp, // ResExp with bits to determine sign and overflow
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output logic [`NF-1:0] ResFrac, // Result fraction
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output logic [`NE-1:0] ResExp, // Result exponent
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output logic Sticky, // sticky bit
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output logic [`NE+1:0] RoundExp,
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output logic Plus1,
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output logic [`FLEN:0] RoundAdd, // how much to add to the result
|
||||
output logic Round, UfLSBRes // bits needed to calculate rounding
|
||||
);
|
||||
logic LSBRes; // bit used for rounding - least significant bit of the normalized sum
|
||||
logic SubBySmallNum, UfSubBySmallNum; // was there supposed to be a subtraction by a small number
|
||||
logic UfCalcPlus1, CalcMinus1, Minus1; // do you add or subtract on from the result
|
||||
logic NormSumSticky; // normalized sum's sticky bit
|
||||
logic UfSticky; // sticky bit for underlow calculation
|
||||
logic NormSumSticky; // normalized sum's sticky bit
|
||||
logic UfSticky; // sticky bit for underlow calculation
|
||||
logic [`NF-1:0] RoundFrac;
|
||||
logic FpRes, IntRes;
|
||||
logic FpRes, IntRes;
|
||||
logic UfRound;
|
||||
logic FpRound, FpLSBRes, FpUfRound;
|
||||
logic CalcPlus1, FpPlus1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user