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Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.

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This commit is contained in:
Ross Thompson 2023-04-17 16:00:02 -05:00
parent fad0366d26
commit 96781e0b2a
2 changed files with 24 additions and 5 deletions
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19
fpga/constraints/small-debug.xdc
View File

@ -38,5 +38,22 @@ set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list mmcm1_locked ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list mmcm_locked ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list c0_init_calib_complete ]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

10
fpga/src/fpgaTopArtyA7.v
View File

@ -167,7 +167,7 @@ module fpgaTop
wire BUSCLK;
wire c0_init_calib_complete;
(* mark_debug = "true" *) wire c0_init_calib_complete;
wire dbg_clk;
wire [511 : 0] dbg_bus;
wire ui_clk_sync_rst;
@ -179,8 +179,10 @@ module fpgaTop
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire mmcm_locked;
(* mark_debug = "true" *) wire mmcm_locked;
wire [11:0] device_temp;
(* mark_debug = "true" *) wire mmcm1_locked;
assign GPIOIN = {28'b0, GPI};
assign GPO = GPIOOUT[4:0];
@ -198,8 +200,8 @@ module fpgaTop
xlnx_mmcm xln_mmcm(.clk_out1(clk167),
.clk_out2(clk200),
.clk_out3(CPUCLK),
.reset(reset),
.locked(),
.reset(1'b0),
.locked(mmcm1_locked),
.clk_in1(default_100mhz_clk));
// SD Card Tristate