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Moved InstrValidNotFLushed to csr including InstrValidM

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This commit is contained in:
David Harris 2022-12-23 00:27:44 -08:00
parent 3b1fe78bdc
commit 0505f1fd37
2 changed files with 5 additions and 6 deletions
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6
pipelined/src/privileged/csr.sv
View File

@ -106,7 +106,7 @@ module csr #(parameter
logic [`XLEN-1:0] TVecAlignedM;
logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = ~StallW & ~FlushW;
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
///////////////////////////////////////////
// MTVAL
@ -212,8 +212,8 @@ module csr #(parameter
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
.STATUS_FS, .BigEndianM);
csrc counters(.clk, .reset,
.StallE, .StallM, .StallW, .FlushM, .FlushW,
.InstrValidM, .LoadStallD, .CSRMWriteM,
.StallE, .StallM, .StallW, .FlushM,
.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,

5
pipelined/src/privileged/csrc.sv
View File

@ -43,8 +43,8 @@ module csrc #(parameter
) (
input logic clk, reset,
input logic StallE, StallM, StallW,
input logic FlushM, FlushW,
input logic InstrValidM, LoadStallD, CSRMWriteM,
input logic FlushM,
input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
input logic BPPredDirWrongM,
input logic BTBPredPCWrongM,
input logic RASPredPCWrongM,
@ -78,7 +78,6 @@ module csrc #(parameter
// Interface signals
flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
// Determine when to increment each counter
assign CounterEvent[0] = 1'b1; // MCYCLE always increments