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IMMU exclude non word-sized accesses

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This commit is contained in:
David Harris 2023-05-01 08:14:19 -07:00
parent bfa35d727b
commit c1786bfec8
2 changed files with 8 additions and 1 deletions
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7
sim/coverage-exclusions-rv64gc.do
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@ -201,6 +201,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $l
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
# IMMU only makes word-sized accesses
set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
set line2 [expr $line + 6 ]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
# Excluding reset and clear for impossible case in the wficountreg in privdec
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2

2
src/mmu/mmu.sv
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@ -128,7 +128,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
// Misaligned faults
always_comb
always_comb // exclusion-tag: immu-wordaccess
case(Size[1:0])
2'b00: DataMisalignedM = 0; // lb, sb, lbu
2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu