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test plan update

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David Harris 2023-04-22 09:38:14 -07:00
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docs/testplans/testplan.md
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# CORE-V Wally Test Plan
# CORE-V Wally Design Verification Test Plan
CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
| Functions | Coverage Method | Status |
| ----------- | ----------- |----|
| Instructions | riscv-arch-test | Pass |
| Privileged Unit | wally-riscv-arch-test | Pass |
| Virtual Memory | wally-riscv-arch-test | Pass |
| PMP | wally-riscv-arch-test | Pass
| Peripherals | wally-riscv-arch-test | Pass |
| Floating-Point | TestFloat | Pass |
| General | Code Coverage | 91% |
| General | Boot Linux in Sim | Pass |
| General | Boot Linux on FPGA | Pass |
The following performance validation is also run:
| Function | Method | Status |
| --- | --- | --- |
| Overall Performance | embench | Pass|
| Overall Performance | coremark | Pass |
| Branch Predictor | *** | Pass |
| Cache Miss Rate | *** | Pass |
CORE-V Wally is tested in the following ways:
* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.