Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Moved C to shift before rather than after using in an iteration

Browse Source
This commit is contained in:
David Harris 2022-09-08 16:05:53 -07:00
parent 1c3064af08
commit 1688d544b9
5 changed files with 23 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
pipelined/src/fpu/fdivsqrtiter.sv
View File

@ -69,7 +69,7 @@ module fdivsqrtiter(
logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b
logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b
logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b
logic [`DIVb-1:0] C[`DIVCOPIES-1:0]; // 0.b
logic [`DIVb-1:0] C[`DIVCOPIES:0]; // 0.b
logic [`DIVb-1:0] initC; // 0.b
logic [`DIVCOPIES-1:0] qn;
@ -93,16 +93,17 @@ module fdivsqrtiter(
if (`RADIX == 2) begin : nextw
assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
// assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
end else begin : nextw
assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
// assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
end
/*
if (`RADIX == 2) assign initC = {1'b1, {(`DIVb-1){1'b0}}}; // *** note that these are preshifted right by r compared to book
else assign initC = {2'b11, {(`DIVb-2){1'b0}}};
// assign initC = 0;
*/
assign initC = 0;
// mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
mux2 #(`DIVb+4) wsmux(NextWSN, {{3{SqrtE&~XZeroE}}, X}, DivStart, WSN);
@ -110,7 +111,7 @@ module fdivsqrtiter(
mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
mux2 #(`DIVb) Cmux(NextC, initC, DivStart, CMux);
mux2 #(`DIVb) Cmux(C[`DIVCOPIES], initC, DivStart, CMux);
flopen #(`DIVb) cflop(clk, DivStart|DivBusy, CMux, C[0]);
// Divisor Selections
@ -128,23 +129,23 @@ module fdivsqrtiter(
if (`RADIX == 2) begin: stage
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM,
.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
.C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
end else begin: stage
logic j1;
assign j1 = (i == 0 & C[0][`DIVb-2] & ~C[0][`DIVb-3]);
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1,
.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]),
.C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
.C(C[i]), .S(S[i]), .SM(SM[i]), .CNext(C[i+1]), .SNext(SNext[i]), .SMNext(SMNext[i]), .qn(qn[i]));
end
if(i<(`DIVCOPIES-1)) begin
if (`RADIX==2)begin
assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0};
assign WC[i+1] = {WCA[i][`DIVb+2:0], 1'b0};
assign C[i+1] = {1'b1, C[i][`DIVb-1:1]};
// assign C[i+1] = {1'b1, C[i][`DIVb-1:1]};
end else begin
assign WS[i+1] = {WSA[i][`DIVb+1:0], 2'b0};
assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0};
assign C[i+1] = {2'b11, C[i][`DIVb-1:2]};
// assign C[i+1] = {2'b11, C[i][`DIVb-1:2]};
end
assign Q[i+1] = QNext[i];
assign QM[i+1] = QMNext[i];

2
pipelined/src/fpu/fdivsqrtpostproc.sv
View File

@ -55,7 +55,7 @@ module fdivsqrtpostproc(
logic wfeq0;
logic [`DIVb+3:0] WCF, WSF;
assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
assign FirstK = ({3'b111, FirstC} & ~({3'b111, FirstC} << 1));
assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);

7
pipelined/src/fpu/fdivsqrtstage2.sv
View File

@ -41,6 +41,7 @@ module fdivsqrtstage2 (
input logic SqrtM,
output logic [`DIVb:0] QNext, QMNext,
output logic qn,
output logic [`DIVb-1:0] CNext,
output logic [`DIVb:0] SNext, SMNext,
output logic [`DIVb+3:0] WSA, WCA
);
@ -51,6 +52,8 @@ module fdivsqrtstage2 (
logic [`DIVb+3:0] F;
logic [`DIVb+3:0] AddIn;
assign CNext = {1'b1, C[`DIVb-1:1]};
// Qmient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// q encoding:
@ -60,7 +63,7 @@ module fdivsqrtstage2 (
// 0010 = -1
// 0001 = -2
qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn);
fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F);
fgen2 fgen2(.sp(qp), .sz(qz), .C(CNext), .S, .SM, .F);
assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}});
// Partial Product Generation
@ -70,7 +73,7 @@ module fdivsqrtstage2 (
// *** dh 8/29/22: will need to trim down to just sotfc
otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext);
sotfc2 sotfc2(.sp(qp), .sz(qz), .C(CNext), .S, .SM, .SNext, .SMNext);
endmodule

7
pipelined/src/fpu/fdivsqrtstage4.sv
View File

@ -38,6 +38,7 @@ module fdivsqrtstage4 (
input logic [`DIVb:0] S, SM,
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb-1:0] C,
output logic [`DIVb-1:0] CNext,
input logic SqrtM, j1,
output logic [`DIVb:0] QNext, QMNext,
output logic qn,
@ -53,6 +54,8 @@ module fdivsqrtstage4 (
logic [4:0] Smsbs;
logic CarryIn;
assign CNext = {2'b11, C[`DIVb-1:2]};
// Qmient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// q encoding:
@ -63,7 +66,7 @@ module fdivsqrtstage4 (
// 0001 = -2
assign Smsbs = S[`DIVb:`DIVb-4];
qsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q);
fgen4 fgen4(.s(q), .C({4'b1111, C}), .S({3'b000, S}), .SM({3'b000, SM}), .F);
fgen4 fgen4(.s(q), .C({4'b1111, CNext}), .S({3'b000, S}), .SM({3'b000, SM}), .F);
always_comb
case (q)
@ -82,7 +85,7 @@ module fdivsqrtstage4 (
csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, C}), .S, .SM, .SNext, .SMNext);
sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, CNext}), .S, .SM, .SNext, .SMNext);
endmodule

2
pipelined/src/fpu/qsel.sv
View File

@ -76,7 +76,7 @@ module fgen2 (
assign SExt = {3'b0, S};
assign SMExt = {3'b0, SM};
assign CExt = {4'hf, C};
assign CExt = {4'hf, C}; // extend C from U0.k to Q4.k
// Generate for both positive and negative bits
assign FP = ~(SExt << 1) & CExt;