Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Another change required for forcing to work correctly with MIE/MIP and SIE/SIP.

Browse Source
This commit is contained in:
Ross Thompson 2022-03-23 10:26:17 -05:00
parent aa60b57fb3
commit af435ab591
1 changed files with 14 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
pipelined/src/privileged/csri.sv
View File

@ -95,20 +95,22 @@ module csri #(parameter
// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
// restricted views of registers
// Add MEIP read-only signal
assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
always_comb begin:regs
// Add MEIP read-only signal
// Machine Mode
assign MIP_REGW = IP_REGW;
assign MIE_REGW = IE_REGW;
MIP_REGW = IP_REGW;
MIE_REGW = IE_REGW;
// Supervisor mode
if (`S_SUPPORTED) begin
assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
end else begin
assign SIP_REGW = 12'b0;
assign SIE_REGW = 12'b0;
// Supervisor mode
if (`S_SUPPORTED) begin
SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
end else begin
SIP_REGW = 12'b0;
SIE_REGW = 12'b0;
end
end
endmodule