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Added fence counter.

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This commit is contained in:
Ross Thompson 2023-03-02 23:29:20 -06:00
parent 3dbfa96aef
commit b19d51b6a2
6 changed files with 19 additions and 13 deletions
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13
src/ieu/controller.sv
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@ -38,7 +38,9 @@ module controller(
output logic [2:0] ImmSrcD, // Type of immediate extension
input logic IllegalIEUFPUInstrD, // Illegal IEU and FPU instruction
output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
// Execute stage control signals
output logic JumpD, // Jump instruction
output logic BranchD, // Branch instruction
// Execute stage control signals
input logic StallE, FlushE, // Stall, flush Execute stage
input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
input logic FWriteIntE, // Write integer register, coming from FPU controller
@ -51,7 +53,8 @@ module controller(
output logic IntDivE, // Integer divide
output logic MDUE, // MDU (multiply/divide) operatio
output logic W64E, // RV64 W-type operation
output logic JumpE, // jump instruction
output logic JumpE, // jump instruction
output logic BranchE, // Branch instruction
output logic SCE, // Store Conditional instruction
output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
// Memory stage control signals
@ -63,9 +66,7 @@ module controller(
output logic RegWriteM, // Instruction writes a register (needed for Hazard unit)
output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
output logic BranchD, BranchE,
output logic JumpD,
output logic FenceM, // Fence instruction
output logic FWriteIntM, // FPU controller writes integer register file
// Writeback stage control signals
input logic StallW, FlushW, // Stall, flush Writeback stage
@ -109,7 +110,7 @@ module controller(
logic IEURegWriteE; // Register write
logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
logic [1:0] AtomicE; // Atomic instruction
logic FenceD, FenceE, FenceM; // Fence instruction
logic FenceD, FenceE; // Fence instruction
logic SFenceVmaD; // sfence.vma instruction
logic IntDivM; // Integer divide instruction

5
src/ieu/ieu.sv
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@ -71,7 +71,8 @@ module ieu (
output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit
output logic MDUStallD, CSRRdStallD, StoreStallD,
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions
output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions
output logic FenceM
);
logic [2:0] ImmSrcD; // Select type of immediate extension
@ -99,7 +100,7 @@ module ieu (
.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD);
datapath dp(
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,

3
src/privileged/csr.sv
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@ -70,6 +70,7 @@ module csr #(parameter
input logic ICacheMiss,
input logic ICacheAccess,
input logic sfencevmaM,
input logic FenceM,
// outputs from CSRs
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
@ -263,7 +264,7 @@ module csr #(parameter
.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
.BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
.InterruptM, .ExceptionM,
.InterruptM, .ExceptionM, .FenceM,
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);

3
src/privileged/csrc.sv
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@ -58,6 +58,7 @@ module csrc #(parameter
input logic sfencevmaM,
input logic InterruptM,
input logic ExceptionM,
input logic FenceM,
input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM,
@ -106,7 +107,7 @@ module csrc #(parameter
assign CounterEvent[17] = ICacheMiss; // instruction cache miss. Miss asserted 1 cycle at start of cache miss
assign CounterEvent[18] = '0; // //// ******** i cache miss cycles
assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM; // CSR writes
assign CounterEvent[20] = '0; // ******** fence.i
assign CounterEvent[20] = FenceM & InstrValidNotFlushedM; // fence.i
assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM; // sfence.vma
assign CounterEvent[22] = InterruptM; // interrupt, InstrValidNotFlushedM will be low
assign CounterEvent[23] = ExceptionM; // exceptions, InstrValidNotFlushedM will be low

3
src/privileged/privileged.sv
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@ -84,6 +84,7 @@ module privileged (
// control outputs
output logic RetM, TrapM, // return instruction, or trap
output logic sfencevmaM, // sfence.vma instruction
input logic FenceM, // fence instruction
output logic BigEndianM, // Use big endian in current privilege mode
// Fault outputs
output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
@ -126,7 +127,7 @@ module privileged (
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
.BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
.sfencevmaM, .ExceptionM,
.sfencevmaM, .ExceptionM, .FenceM,
.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,

5
src/wally/wallypipelinedcore.sv
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@ -161,6 +161,7 @@ module wallypipelinedcore (
logic FCvtIntE;
logic CommittedF;
logic BranchD, BranchE, JumpD, JumpE;
logic FenceM;
// instruction fetch unit: PC, branch prediction, instruction cache
ifu ifu(.clk, .reset,
@ -207,7 +208,7 @@ module wallypipelinedcore (
// hazards
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD);
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .FenceM, .StoreStallD);
lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
@ -285,7 +286,7 @@ module wallypipelinedcore (
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF,
.InstrM, .CSRReadValW, .UnalignedPCNextF,
.RetM, .TrapM, .sfencevmaM,
.RetM, .TrapM, .sfencevmaM, .FenceM,
.InstrValidM, .CommittedM, .CommittedF,
.FRegWriteM, .LoadStallD, .StoreStallD,
.BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,