forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
4fbda554ee
2
pipelined/src/cache/cache.sv
vendored
2
pipelined/src/cache/cache.sv
vendored
@ -132,7 +132,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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.Invalidate(InvalidateCache));
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if(NUMWAYS > 1) begin:vict
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cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage));
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid);
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end else assign VictimWay = 1'b1; // one hot.
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assign CacheHit = | HitWay;
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assign VictimDirty = | VictimDirtyWay;
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168
pipelined/src/cache/cachereplacementpolicy.sv
vendored
168
pipelined/src/cache/cachereplacementpolicy.sv
vendored
@ -3,6 +3,7 @@
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//
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// Written: ross1728@gmail.com July 20, 2021
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// Implements Pseudo LRU
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// Tested for Powers of 2.
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//
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//
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// A component of the Wally configurable RISC-V project.
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@ -35,30 +36,35 @@ module cachereplacementpolicy
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input logic [NUMWAYS-1:0] HitWay,
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output logic [NUMWAYS-1:0] VictimWay,
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input logic [SETLEN-1:0] RAdr,
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input logic LRUWriteEn);
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input logic LRUWriteEn, SetValid);
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logic [NUMWAYS-2:0] LRUEn, LRUMask;
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logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
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logic [NUMWAYS-2:0] LineReplacementBits;
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logic [NUMWAYS-2:0] NewReplacement;
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logic [NUMWAYS-2:0] NewReplacementD;
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logic [SETLEN+OFFSETLEN-1:OFFSETLEN] PAdrD;
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logic [SETLEN-1:0] RAdrD;
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logic LRUWriteEnD;
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logic [NUMWAYS-1:0] Way;
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localparam LOGNUMWAYS = $clog2(NUMWAYS);
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localparam LEN = NUMWAYS-1;
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logic [LOGNUMWAYS-1:0] HitWayEnc;
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logic [LEN-1:0] HitWayExpand;
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logic [LOGNUMWAYS-1:0] WayEncoded;
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logic [NUMWAYS-2:0] WayExpanded;
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genvar row;
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logic [NUMWAYS-2:0] cEn;
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/* verilator lint_off UNOPTFLAT */
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// Ross: For some reason verilator does not like this. I checked and it is not a circular path.
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logic [NUMWAYS-2:0] MuxEnables;
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logic [LOGNUMWAYS-1:0] Intermediate [NUMWAYS-2:0];
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/* verilator lint_on UNOPTFLAT */
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function integer log2 (integer value);
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for (log2=0; value>0; log2=log2+1)
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value = value>>1;
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return log2;
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endfunction // log2
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// proposed generic solution
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/* -----\/----- EXCLUDED -----\/-----
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binencoder #(NUMWAYS) encoder(HitWay, HitWayEnc);
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// mux between HitWay on a hit and victimway on a miss.
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mux2 #(NUMWAYS) WayMux(HitWay, VictimWay, SetValid, Way);
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binencoder #(NUMWAYS) encoder(Way, WayEncoded);
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// bit duplication
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// expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
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@ -66,22 +72,22 @@ module cachereplacementpolicy
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localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
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localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
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localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
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assign HitWayExpand[StartIndex : EndIndex] = {{DuplicationFactor}{HitWayEnc[row]}};
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assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
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end
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genvar r, a,s;
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assign cEn[NUMWAYS-2] = '1;
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genvar r, a, s;
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assign MuxEnables[NUMWAYS-2] = '1;
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for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
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localparam p = NUMWAYS - s;
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localparam g = $clog2(p);
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localparam t0 = s - g;
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localparam p = NUMWAYS - s - 1;
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localparam g = log2(p);
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localparam t0 = s - p;
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localparam t1 = t0 - 1;
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localparam r = LOGNUMWAYS - g;
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assign cEn[t0] = cEn[s] & ~HitWayEnc[r];
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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assign MuxEnables[t0] = MuxEnables[s] & ~WayEncoded[r];
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assign MuxEnables[t1] = MuxEnables[s] & WayEncoded[r];
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end
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, ~HitWayExpand, cEn, NewReplacement);
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, ~WayExpanded, MuxEnables, NewReplacement);
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always_ff @(posedge clk) begin
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if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
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@ -94,113 +100,19 @@ module cachereplacementpolicy
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end
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end
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end
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localparam HalfPoint = (2**$clog2(NUMWAYS)) / 2;
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logic [NUMWAYS-2:0] ivec;
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assign ivec[HalfPoint-1:0] = LineReplacementBits[HalfPoint-1:0];
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for(r = NUMWAYS-2; r >= HalfPoint; r--) begin
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for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin
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localparam p = NUMWAYS - s - 1;
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localparam t0 = s - p;
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localparam t1 = t0 - 1;
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assign Intermediate[s] = LineReplacementBits[s] ? Intermediate[t1] : Intermediate[t0];
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end
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for(s = NUMWAYS/2-1; s >= 0; s--) begin
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localparam int1 = (NUMWAYS/2-1-s)*2 + 1;
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localparam int0 = int1-1;
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assign Intermediate[s] = LineReplacementBits[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
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end
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assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
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assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
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assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
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assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
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-----/\----- EXCLUDED -----/\----- */
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// *** high priority to clean up
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initial begin
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assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
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end
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// Replacement Bits: Register file
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// Needs to be resettable for simulation, but could omit reset for synthesis ***
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always_ff @(posedge clk) begin
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if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
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if(ce) begin
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if (LRUWriteEn) begin
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ReplacementBits[RAdr] <= NewReplacement;
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LineReplacementBits <= #1 NewReplacement;
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end else begin
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LineReplacementBits <= #1 ReplacementBits[RAdr];
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end
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end
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end
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genvar index;
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if(NUMWAYS == 2) begin : PseudoLRU
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assign LRUEn[0] = 1'b0;
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assign NewReplacement[0] = HitWay[1];
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assign VictimWay[1] = ~LineReplacementBits[0];
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assign VictimWay[0] = LineReplacementBits[0];
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end else if (NUMWAYS == 4) begin : PseudoLRU
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// 1 hot encoding for VictimWay; LRU = LineReplacementBits
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//| LRU 2 | LRU 1 | LRU 0 | VictimWay
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//+-------+-------+-------+-----------
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//| 1 | - | 1 | 0001
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//| 1 | - | 0 | 0010
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//| 0 | 1 | - | 0100
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//| 0 | 0 | - | 1000
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assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
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assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
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assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
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assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
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// New LRU bits which are updated is function only of the HitWay.
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// However the not updated bits come from the old LRU.
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assign LRUEn[2] = |HitWay;
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assign LRUEn[1] = HitWay[3] | HitWay[2];
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assign LRUEn[0] = HitWay[1] | HitWay[0];
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assign LRUMask[2] = HitWay[1] | HitWay[0];
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assign LRUMask[1] = HitWay[2];
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assign LRUMask[0] = HitWay[0];
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement);
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end
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/* *** 8-way not yet working - look for a general way to write this for all NUMWAYS
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else if (NUMWAYS == 8) begin : PseudoLRU
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// selects
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assign LRUEn[6] = 1'b1;
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assign LRUEn[5] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4];
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assign LRUEn[4] = HitWay[7] | HitWay[6];
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assign LRUEn[3] = HitWay[5] | HitWay[4];
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assign LRUEn[2] = HitWay[3] | HitWay[2] | HitWay[1] | HitWay[0];
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assign LRUEn[1] = HitWay[3] | HitWay[2];
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assign LRUEn[0] = HitWay[1] | HitWay[0];
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// mask
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assign LRUMask[6] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4];
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assign LRUMask[5] = HitWay[7] | HitWay[6];
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assign LRUMask[4] = HitWay[7];
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assign LRUMask[3] = HitWay[5];
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assign LRUMask[2] = HitWay[3] | HitWay[2];
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assign LRUMask[1] = HitWay[2];
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assign LRUMask[0] = HitWay[0];
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for(index = 0; index < NUMWAYS-1; index++)
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assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
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assign EncVicWay[2] = LineReplacementBits[6];
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assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2];
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assign EncVicWay[0] = LineReplacementBits[6] ? LineReplacementBits[5] ? LineReplacementBits[4] : LineReplacementBits[3] :
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LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0];
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onehotdecoder #(3)
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waydec(.bin(EncVicWay),
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.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
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VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
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end */
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decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay);
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endmodule
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