Cleaned up branch predictor performance counters.

config/rv32gc/wally-config.vh

@@ -134,7 +134,7 @@
 
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
+`define BPRED_SIZE 16
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0

sim/sim-imperas

@@ -29,4 +29,4 @@
 IMPERAS_TOOLS=$(pwd)/imperas.ic \
 OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
 TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/Lee.S/  \
-vsim  -do "do wally-pipelined-imperas.do rv64gc"
+vsim  -do "do wally-imperas.do rv64gc"

src/ifu/bpred/bpred.sv

@@ -59,7 +59,6 @@ module bpred (
   input logic [`XLEN-1:0]  IEUAdrM,                   // The branch/jump target address
   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
-  output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
   output logic             BPWrongE,              // Prediction is wrong
@@ -196,7 +195,6 @@ module bpred (
   else	assign NextValidPCE = PCE;
 
   if(`ZICOUNTERS_SUPPORTED) begin
-    logic 					JumpOrTakenBranchE;
     logic [`XLEN-1:0] 	    RASPCD, RASPCE;
     logic 					BTBPredPCWrongE, RASPredPCWrongE;	
     // performance counters
@@ -209,13 +207,10 @@ module bpred (
     // could be wrong or the fall through address selected for branch predict not taken.
     // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
     // both without the above inaccuracies.
+	// **** use BTAWrongM from BTB.
     assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 
-    assign JumpOrTakenBranchE = (BranchE & PCSrcE) | JumpE;
-    
-    flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
-
     flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
     flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
     flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
@@ -223,7 +218,7 @@ module bpred (
 				  {BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM});
     
   end else begin
-    assign {BTBPredPCWrongM, RASPredPCWrongM, JumpOrTakenBranchM} = '0;
+    assign {BTBPredPCWrongM, RASPredPCWrongM} = '0;
   end
 
   // **** Fix me

src/ifu/ifu.sv

@@ -65,7 +65,6 @@ module ifu (
   output logic [`XLEN-1:0] 	PCM,                                      // Memory stage instruction address
   // branch predictor
   output logic [3:0] 		InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-  output logic              JumpOrTakenBranchM,
   output logic 				BPDirPredWrongM,                      // Prediction direction is wrong
   output logic 				BTBPredPCWrongM,                          // Prediction target wrong
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
@@ -88,7 +87,7 @@ module ifu (
   input logic [1:0] 		STATUS_MPP,                               // Status CSR: previous machine privilege level
   input logic               sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
   output logic 				ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
-  output logic              InstrUpdateDAF,                        // ITLB hit needs to update dirty or access bits
+  output logic              InstrUpdateDAF,                           // ITLB hit needs to update dirty or access bits
   input  var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],         // PMP configuration from privileged unit
   input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],  // PMP address from privileged unit
   output logic 				InstrAccessFaultF,                        // Instruction access fault 
@@ -331,7 +330,7 @@ module ifu (
                 .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
                 .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPWrongM,
+                .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
                 .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM);
 
   end else begin : bpred

src/privileged/csr.sv

@@ -63,7 +63,6 @@ module csr #(parameter
   input  logic             IClassWrongM,
   input  logic             BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,
-  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,
   input  logic             DCacheAccess,
   input  logic             ICacheMiss,
@@ -259,7 +258,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
-      .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .JumpOrTakenBranchM, .BPWrongM,
+      .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,

src/privileged/csrc.sv

@@ -50,7 +50,6 @@ module csrc #(parameter
   input  logic 	            IClassWrongM,
   input  logic              BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]        InstrClassM,
-  input  logic              JumpOrTakenBranchM,                               // actual instruction class
   input  logic 	            DCacheMiss,
   input  logic 	            DCacheAccess,
   input  logic 	            ICacheMiss,
@@ -86,10 +85,10 @@ module csrc #(parameter
     assign CounterEvent[`COUNTERS-1:3] = 0;
   end else begin: cevent                                                                // User-defined counters
     assign CounterEvent[3] = LoadStallM & InstrValidNotFlushedM;                        // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[4] = BPDirPredWrongM & InstrValidNotFlushedM;               // Branch predictor wrong direction
+    assign CounterEvent[4] = BPDirPredWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
     assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
     assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
-    assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM;                // jump or taken branch instructions
+    assign CounterEvent[7] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM;  // jump and not return instructions
     assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong

src/privileged/privileged.sv

@@ -52,7 +52,6 @@ module privileged (
   input  logic 		         IClassWrongM,              // branch predictor guessed wrong instruction class
   input  logic             BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,                               // actual instruction class
-  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,                                // data cache miss
   input  logic             DCacheAccess,                              // data cache accessed (hit or miss)
   input  logic             ICacheMiss,                                // instruction cache miss
@@ -126,7 +125,7 @@ module privileged (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
     .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
-    .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
+    .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,

src/wally/wallypipelinedcore.sv

@@ -160,7 +160,6 @@ module wallypipelinedcore (
   logic                          BigEndianM;
   logic                          FCvtIntE;
   logic                          CommittedF;
-  logic 						 JumpOrTakenBranchM;
   logic 						 BranchD, BranchE, JumpD, JumpE;
   
   // instruction fetch unit: PC, branch prediction, instruction cache
@@ -176,7 +175,7 @@ module wallypipelinedcore (
     .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE,  .BPWrongM, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM, .JumpOrTakenBranchM,
+    .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM,
     // Faults out
     .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
@@ -291,7 +290,7 @@ module wallypipelinedcore (
       .FRegWriteM, .LoadStallD,
       .BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,
       .RASPredPCWrongM, .IClassWrongM,
-      .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
+      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,