forked from Github_Repos/cvw
Keep around the old gshare.
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2224679694
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@ -140,7 +140,7 @@
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`define PLIC_UART_ID 10
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`define BPRED_ENABLED 1
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`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE
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`define BPTYPE "BPOLDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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@ -113,6 +113,11 @@ module bpred (
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.BranchInstrF(BPInstrClassF[0]), .BranchInstrD(BPInstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
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.BranchInstrW(InstrClassW[0]), .PCSrcE);
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end else if (`BPTYPE == "BPOLDGSHARE") begin:Predictor
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oldgsharePredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
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.InstrClassE, .PCSrcE);
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end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
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// *** Fix me
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/* -----\/----- EXCLUDED -----\/-----
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@ -31,22 +31,21 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module gsharePredictor
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module oldgsharePredictor
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(input logic clk,
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input logic reset,
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input logic StallF, StallE,
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input logic [`XLEN-1:0] PCNextF,
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output logic [1:0] BPPredF,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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output logic [1:0] DirPredictionF,
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// update
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input logic [4:0] InstrClassE,
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input logic [4:0] BPInstrClassE,
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input logic [4:0] BPInstrClassD,
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input logic [4:0] BPInstrClassF,
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input logic BPPredDirWrongE,
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output logic DirPredictionWrongE,
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input logic [`XLEN-1:0] PCE,
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input logic PCSrcE,
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input logic [1:0] UpdateBPPredE
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input logic PCSrcE
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);
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logic [`BPRED_SIZE+1:0] GHR, GHRNext;
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@ -57,6 +56,8 @@ module gsharePredictor
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logic BPClassRightNonCFI;
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logic BPClassRightBPWrong;
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logic BPClassRightBPRight;
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logic [1:0] DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionE;
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logic [6:0] GHRMuxSel;
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logic GHRUpdateEN;
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@ -65,8 +66,8 @@ module gsharePredictor
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assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
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assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
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assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE;
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assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE;
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assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
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assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
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// GHR update selection, 1 hot encoded.
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@ -88,7 +89,7 @@ module gsharePredictor
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7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
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7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
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7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
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7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], BPPredF[1]}; // speculative update
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7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
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default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
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endcase
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end
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@ -114,11 +115,20 @@ module gsharePredictor
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.reset(reset),
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//.RA1(GHR[`BPRED_SIZE-1:0]),
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.ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
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.rd1(BPPredF),
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.rd1(DirPredictionF),
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.ren1(~StallF),
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.wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
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.wd2(UpdateBPPredE),
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.wd2(NewDirPredictionE),
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.wen2(PHTUpdateEN),
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.bwe2(2'b11));
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
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endmodule // gsharePredictor
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