Removed unused DivSE from FPU

2022-12-26 07:29:19 -08:00 · 2022-12-26 07:29:19 -08:00 · a7204c9012
commit a7204c9012
parent fb0b2d4227
1 changed files with 1 additions and 1 deletions
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@ -129,7 +129,7 @@ module fpu (
   //divide signals
   logic [`DIVb:0]      QmM;
   logic [`NE+1:0]      QeE, QeM; 
-   logic                DivSE, DivSM;
+   logic                DivSM;
 //   logic                DivDoneM;
   logic                FDivDoneE, IFDivStartE;