forked from Github_Repos/cvw
Merge pull request #170 from ross144/main
Fixed issue 148 and problems with i/d cache address loggers.
This commit is contained in:
David Harris
GitHub
commit
cac9d31696
2
src/cache/cachefsm.sv
vendored
2
src/cache/cachefsm.sv
vendored
@ -135,7 +135,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
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end
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// com back to CPU
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
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assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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@ -33,7 +33,8 @@ module ahbcacheinterface #(
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parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
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parameter AHBWLOGBWPL, // Log2 of ^
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parameter LINELEN, // Number of bits in cacheline
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parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
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parameter READ_ONLY_CACHE
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)(
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input logic HCLK, HRESETn,
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// bus interface controls
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@ -115,7 +116,7 @@ module ahbcacheinterface #(
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flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm(
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buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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@ -33,7 +33,8 @@
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// HCLK and clk must be the same clock!
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module buscachefsm #(
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parameter BeatCountThreshold, // Largest beat index
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parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
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parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE
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parameter READ_ONLY_CACHE
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)(
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input logic HCLK,
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input logic HRESETn,
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@ -121,7 +122,7 @@ module buscachefsm #(
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(CurrState == DATA_PHASE) |
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(CurrState == CACHE_FETCH & ~HREADY) |
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(CurrState == CACHE_WRITEBACK & ~HREADY);
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assign BusCommitted = CurrState != ADR_PHASE;
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assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3);
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) |
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@ -251,7 +251,7 @@ module ifu (
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.NextSet(PCSpillNextF[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
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ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW)
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ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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@ -275,7 +275,7 @@ module lsu (
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.FetchBuffer, .CacheBusRW,
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface(
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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@ -29,9 +29,9 @@
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`include "tests.vh"
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`define PrintHPMCounters 1
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`define BPRED_LOGGER 1
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`define I_CACHE_ADDR_LOGGER 1
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`define D_CACHE_ADDR_LOGGER 1
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`define BPRED_LOGGER 0
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`define I_CACHE_ADDR_LOGGER 0
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`define D_CACHE_ADDR_LOGGER 0
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module testbench;
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parameter DEBUG=0;
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@ -169,7 +169,8 @@ logic [3:0] dummy;
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logic InitializingMemories;
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integer ResetCount, ResetThreshold;
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logic InReset;
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logic Begin;
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// instantiate device to be tested
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assign GPIOIN = 0;
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assign UARTSin = 1;
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@ -417,7 +418,7 @@ logic [3:0] dummy;
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if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed;
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logic StartSampleDelayed, BeginDelayed;
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logic EndSampleFirst, EndSampleDelayed;
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logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
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@ -476,8 +477,11 @@ logic [3:0] dummy;
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assign StartSampleFirst = InReset;
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
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assign Begin = StartSampleFirst & ~ BeginDelayed;
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end
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always @(negedge clk) begin
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@ -528,7 +532,7 @@ logic [3:0] dummy;
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// initialize the branch predictor
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if (`BPRED_SUPPORTED == 1) begin
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if (`BPRED_SUPPORTED) begin
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integer adrindex;
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always @(*) begin
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@ -551,55 +555,63 @@ logic [3:0] dummy;
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end
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if (`I_CACHE_ADDR_LOGGER == 1) begin
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if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin
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int file;
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string LogFile;
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logic resetD, resetEdge;
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logic Enable;
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assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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LogFile = $psprintf("ICache.log");
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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string HitMissString;
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assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : "M";
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(~dut.core.StallD & ~dut.core.FlushD) begin
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$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
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if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
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if(Enable) begin // only log i cache reads
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$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (`D_CACHE_ADDR_LOGGER == 1) begin
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if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin
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int file;
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string LogFile;
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logic resetD, resetEdge;
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string HitMissString;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : "M";
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initial begin
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LogFile = $psprintf("DCache.log");
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
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if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
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$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h R %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
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$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h W %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
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$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h A %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
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$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h F %s\n", dut.core.lsu.PAdrM, HitMissString);
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end
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (`BPRED_SUPPORTED == 1) begin
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if (`BPRED_SUPPORTED) begin
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if (`BPRED_LOGGER) begin
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string direction;
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int file;
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