forked from Github_Repos/cvw
Merge branch 'main' of github.com:ross144/cvw
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commit
f2edf0ff86
@ -30,6 +30,8 @@
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`define PrintHPMCounters 1
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`define BPRED_LOGGER 1
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`define I_CACHE_ADDR_LOGGER 1
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`define D_CACHE_ADDR_LOGGER 1
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module testbench;
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parameter DEBUG=0;
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@ -546,9 +548,57 @@ logic [3:0] dummy;
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end
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end
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end
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end
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if (`I_CACHE_ADDR_LOGGER == 1) begin
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int file;
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string LogFile;
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logic resetD, resetEdge;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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LogFile = $psprintf("ICache.log");
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file = $fopen(LogFile, "w");
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(~dut.core.StallD & ~dut.core.FlushD) begin
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$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (`D_CACHE_ADDR_LOGGER == 1) begin
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int file;
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string LogFile;
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logic resetD, resetEdge;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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LogFile = $psprintf("DCache.log");
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file = $fopen(LogFile, "w");
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
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$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
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end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
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$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
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end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
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$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
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end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
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$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
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end
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (`BPRED_SUPPORTED == 1) begin
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if (`BPRED_LOGGER) begin
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string direction;
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