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Fixed backward mux in fdivsqrtstage2

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This commit is contained in:
David Harris 2022-12-31 06:55:20 -08:00
parent 7c7d40ad63
commit c1689b54bb
1 changed files with 2 additions and 3 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -68,12 +68,11 @@ module fdivsqrtstage2 (
always_comb
if (up) Dsel = DBar;
else if (uz) Dsel = '0;
else Dsel = {3'b000, 1'b1, D}; // un
else Dsel = {4'b0001, D}; // un
// Partial Product Generation
// WSA, WCA = WS + WC - qD
mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn);
//assign AddIn = SqrtE ? F : Dsel;
mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
assign WSNext = WSA << 1;
assign WCNext = WCA << 1;