fixed -1 issue in division

pipelined/src/fpu/divsqrt.sv

@@ -57,14 +57,15 @@ module divsqrt(
   logic [`DIVb+3:0]  WS, WC;
   logic [`DIVb+3:0] StickyWSA;
   logic [`DIVb:0] X;
+  logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVN-2:0] Dpreproc;
   logic [`DURLEN-1:0] Dur;
   logic NegSticky;
 
   srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
 
-  srtfsm srtfsm(.reset, .XsE, .SqrtE, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE,
+  srtfsm srtfsm(.reset, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE,
                .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM));
-  srt srt(.clk, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
+  srt srt(.clk, .D, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
                 .StickyWSA, .DivBusy, .Qm(QmM));
 endmodule

pipelined/src/fpu/qsel.sv

@@ -158,7 +158,7 @@ module qsel4 (
           7: if(w2>=22)      QSel4[i] = 4'b1000; // was 24
             else if(w2>=8)   QSel4[i] = 4'b0100; 
             else if(w2>=-8)  QSel4[i] = 4'b0000; 
-            else if(w2>=-23) QSel4[i] = 4'b0010; // was -24
+            else if(w2>=-23) QSel4[i] = 4'b0010; // was -24 ***use -22
             else             QSel4[i] = 4'b0001; 
         endcase
       end

pipelined/src/fpu/srt.sv

@@ -42,6 +42,7 @@ module srt(
   input  logic [`DIVN-2:0] Dpreproc,
   input  logic NegSticky,
   output logic [`DIVb-(`RADIX/4):0] Qm,
+  output logic [`DIVN-2:0]  D, // U0.N-1
   output logic [`DIVb+3:0]  NextWSN, NextWCN,
   output logic [`DIVb+3:0]  StickyWSA,
   output logic [`DIVb+3:0]  FirstWS, FirstWC
@@ -70,7 +71,6 @@ module srt(
   logic [`DIVb-1:0] C[`DIVCOPIES-1:0]; // 0.b
  /* verilator lint_on UNOPTFLAT */
   logic [`DIVb+3:0]  WSN, WCN; // Q4.N-1
-  logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVb+3:0]  DBar, D2, DBar2; // Q4.N-1
   logic [`DIVb:0] QMMux;
   logic [`DIVb-1:0] NextC;

pipelined/src/fpu/srtfsm.sv

@@ -40,8 +40,10 @@ module srtfsm(
   input  logic DivStart, 
   input  logic XsE,
   input  logic SqrtE,
+  input  logic SqrtM,
   input  logic StallE,
   input  logic StallM,
+  input logic [`DIVN-2:0]  D, // U0.N-1
   input  logic [`DIVb+3:0] StickyWSA,
   input  logic [`DURLEN-1:0] Dur,
   output logic [`DURLEN-1:0] EarlyTermShiftE,
@@ -58,18 +60,22 @@ module srtfsm(
   logic WZero;
   //logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
   logic [`DIVb+3:0] W;
-
   //flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
   assign DivBusy = (state == BUSY);
-  assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
   // calculate sticky bit
   //    - there is a chance that a value is subtracted infinitly, resulting in an exact QM result
   //      this is only a problem on radix 2 (and pssibly maximally redundant 4) since minimally redundant
   //      radix-4 division can't create a QM that continually adds 0's
-  if (`RADIX == 2)
-    assign DivSE = |W&~(StickyWSA == WS);
-  else
+  if (`RADIX == 2) begin
+    logic [`DIVb+3:0] FNext;
+    assign FNext = SqrtM ? 0 : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
+    // *** |... for continual -1 is not efficent fix - also only needed for radix-2
+    assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0})|((NextWSN+NextWCN+FNext)==0);
+    assign DivSE = |W&~((W+FNext)==0); //***not efficent fix ==
+  end else begin
+    assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
     assign DivSE = |W;
+  end
   assign DivDone = (state == DONE);
   assign W = WC+WS;
   assign NegSticky = W[`DIVb+3];