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added memories (not tested)

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This commit is contained in:
Madeleine Masser-Frye 2023-02-01 06:08:27 +00:00
parent c78adbb8e7
commit ad6d7eb5e2
3 changed files with 6 additions and 2 deletions
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2
pipelined/config/shared/wally-shared.vh
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@ -34,7 +34,7 @@
`define ZBS_SUPPORTED 0
// Memory synthesis configuration
`define USE_SRAM 0
`define USE_SRAM 1
// shared constants
`include "wally-constants.vh"

2
pipelined/src/generic/mem/ram1p1rwbe.sv
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@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));

4
synthDC/.synopsys_dc.setup
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@ -48,6 +48,10 @@ set cache_read $cache_write
lappend search_path ./scripts
lappend search_path ./hdl
lappend search_path ./mapped
set memory /home/jstine/WallyMem/rv64gc/
lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
# Set up User Information
set company "Oklahoma State University"