Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.

Browse Source
This commit is contained in:
Ross Thompson 2022-09-29 18:37:34 -05:00
parent 47e936cab3
commit e6db1c5cf8
2 changed files with 23 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
pipelined/src/ebu/controllerinputstage.sv
View File

@ -36,17 +36,17 @@
`include "wally-config.vh"
module controllerinputstage
module controllerinputstage #(parameter SAVE_ENABLED = 1)
(input logic HCLK,
input logic HRESETn,
input logic Save, Restore, Disable,
output logic Request,
// controller input
input logic HWRITEin,
input logic [2:0] HSIZEin,
input logic [2:0] HBURSTin,
input logic [1:0] HTRANSin,
input logic [`PA_BITS-1:0] HADDRin,
input logic HWRITEIn,
input logic [2:0] HSIZEIn,
input logic [2:0] HBURSTIn,
input logic [1:0] HTRANSIn,
input logic [`PA_BITS-1:0] HADDRIn,
output logic HREADYOut,
// controller output
output logic HWRITEOut,
@ -54,7 +54,7 @@ module controllerinputstage
output logic [2:0] HBURSTOut,
output logic [1:0] HTRANSOut,
output logic [`PA_BITS-1:0] HADDROut,
input logic HREADYin
input logic HREADYIn
);
logic HWRITESave;
@ -63,16 +63,24 @@ module controllerinputstage
logic [1:0] HTRANSSave;
logic [`PA_BITS-1:0] HADDRSave;
if (SAVE_ENABLED) begin
flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
{HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
{HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
Restore,
{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
end else begin
assign HWRITEOut = HWRITEIn;
assign HSIZEOut = HSIZEIn;
assign HBURSTOut = HBURSTIn;
assign HTRANSOut = HTRANSIn;
assign HADDROut = HADDRIn;
end
assign Request = HTRANSOut != 2'b00;
assign HREADYOut = HREADYin & ~Disable;
assign HREADYOut = HREADYIn & ~Disable;
endmodule

10
pipelined/src/ebu/ebu.sv
View File

@ -111,17 +111,17 @@ module ebu
// input stage IFU
controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
.Request(IFUReq),
.HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
.HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
// input stage LSU
// LSU always has priority so there should never be a need to save and restore the address phase inputs.
controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
controllerinputstage #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
.Request(LSUReq),
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
.HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
// output mux //*** rewrite for general number of controllers.
assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;