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IEU comment cleanup

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This commit is contained in:
David Harris 2023-01-17 10:51:44 -08:00
parent 77766a6dac
commit 555fee94fa
7 changed files with 24 additions and 24 deletions
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2
pipelined/src/ieu/comparator.sv
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@ -87,7 +87,7 @@ module comparator_sub #(parameter WIDTH=64) (
assign flags = {eq, lt, ltu};
endmodule
// *** eventually substitute comparator_flip, which gives slightly better synthesis
// comparator_flip, gives slightly better synthesis
module comparator #(parameter WIDTH=64) (
input logic [WIDTH-1:0] a, b,
output logic [2:0] flags);

10
pipelined/src/ieu/controller.sv
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@ -36,8 +36,8 @@ module controller(
input logic StallD, FlushD, // Stall, flush Decode stage
input logic [31:0] InstrD, // Instruction in Decode stage
output logic [2:0] ImmSrcD, // Type of immediate extension
input logic IllegalIEUInstrFaultD, // Illegal instruction ***
output logic IllegalBaseInstrFaultD, // ***
input logic IllegalIEUInstrFaultD, // Illegal IEU instruction
output logic IllegalBaseInstrFaultD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
// Execute stage control signals
input logic StallE, FlushE, // Stall, flush Execute stage
input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
@ -107,10 +107,10 @@ module controller(
logic unused;
logic BranchFlagE; // Branch flag to use (chosen between eq or lt)
logic IEURegWriteE; // Register write
logic IllegalERegAdrD; // ***
logic [1:0] AtomicE; // *** Atomic instruction
logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
logic [1:0] AtomicE; // Atomic instruction
logic FenceD, FenceE, FenceM; // Fence instruction
logic SFenceVmaD; // *** Fence virtual memory address ***?
logic SFenceVmaD; // sfence.vma instruction
logic IntDivM; // Integer divide instruction

4
pipelined/src/ieu/datapath.sv
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@ -71,11 +71,11 @@ module datapath (
// Fetch stage signals
// Decode stage signals
logic [`XLEN-1:0] R1D, R2D; // Read data from Rs1 (RD1), Rs2 (RD2)
logic [`XLEN-1:0] ImmExtD; // Extended immediate in Decode stage *** According to Figure 4.12, should be ImmExtD
logic [`XLEN-1:0] ImmExtD; // Extended immediate in Decode stage
logic [4:0] RdD; // Destination register in Decode stage
// Execute stage signals
logic [`XLEN-1:0] R1E, R2E; // Source operands read from register file
logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage ***According to Figure 4.12, should be ImmExtE
logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage
logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands
logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), computed address *** According to Figure 4.12, IEUResultE should be called IEUAdrE
// Memory stage signals

2
pipelined/src/ieu/extend.sv
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@ -32,7 +32,7 @@
module extend (
input logic [31:7] InstrD, // All instruction bits except opcode (lower 7 bits)
input logic [2:0] ImmSrcD, // Select what kind of extension to perform
output logic [`XLEN-1:0 ] ImmExtD); // Extended immediate ***According to Figure 4.12, should be ImmExtD
output logic [`XLEN-1:0 ] ImmExtD); // Extended immediate
localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug

4
pipelined/src/ieu/forward.sv
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@ -34,8 +34,8 @@ module forward(
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
input logic MemReadE, MDUE, CSRReadE, // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE)
input logic RegWriteM, RegWriteW, // Instruction in Memory or Writeback stage writes register file
input logic FCvtIntE, // *** FPU (Floating-point unit) converting float to int
input logic SCE, // *** Store Conditional instruction
input logic FCvtIntE, // FPU convert float to int
input logic SCE, // Store Conditional instruction
// Forwarding controls
output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers
output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD // Stall due to conversion, load, multiply/divide, CSR read

24
pipelined/src/ieu/ieu.sv
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@ -33,7 +33,7 @@ module ieu (
// Decode stage signals
input logic [31:0] InstrD, // Instruction
input logic IllegalIEUInstrFaultD, // Illegal instruction
output logic IllegalBaseInstrFaultD, // ***
output logic IllegalBaseInstrFaultD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
// Execute stage signals
input logic [`XLEN-1:0] PCE, // PC
input logic [`XLEN-1:0] PCLinkE, // PC + 4
@ -44,31 +44,31 @@ module ieu (
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
output logic [4:0] RdE, // Destination register
// Memory stage signals
input logic SquashSCW, // From LSU ***
input logic SquashSCW, // Squash store conditional, from LSU
output logic [1:0] MemRWM, // Read/write control goes to LSU
output logic [1:0] AtomicM, // Atomic control goes to LSU
output logic [`XLEN-1:0] WriteDataM, // Write data to LSU
output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU
output logic [`XLEN-1:0] SrcAM, // ALU SrcA to Privileged unit and FPU
output logic [4:0] RdM, // Destination register
input logic [`XLEN-1:0] FIntResM, // ***
input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp)
output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
output logic InstrValidM, // Instruction is valid
// Writeback stage signals
input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result *** why F?
input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt
input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // CSR read value, MDU (multiply/divide unit) result
input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result ***
input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result
input logic FCvtIntW, // FPU converts float to int
output logic [4:0] RdW, // Destination register
input logic [`XLEN-1:0] ReadDataW, // LSU's read data
// Hazard unit signals
input logic StallD, StallE, StallM, StallW, // Final stall signals ***
input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit
input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
output logic FCvtIntStallD, LoadStallD, // Intermediate stall signals ***
output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit
output logic MDUStallD, CSRRdStallD, StoreStallD,
output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE)
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction ***
output logic CSRWriteFenceM // CSR write is a fence instruction ***
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions
);
logic [2:0] ImmSrcD; // Select type of immediate extension
@ -77,8 +77,8 @@ module ieu (
logic ALUSrcAE, ALUSrcBE; // ALU source operands
logic [2:0] ResultSrcW; // Source of result in Writeback stage
logic ALUResultSrcE; // ALU result
logic SCE; // Store Conditional instruction ***
logic FWriteIntM; // FPU writing to integer register file ***
logic SCE; // Store Conditional instruction
logic FWriteIntM; // FPU writing to integer register file
logic IntDivW; // Integer divide instruction
// forwarding signals
@ -88,7 +88,7 @@ module ieu (
logic MemReadE, CSRReadE; // Load, CSRRead instruction
logic JumpE; // Jump instruction
logic BranchSignedE; // Branch does signed comparison on operands
logic MDUE; // Multiply/divide instruction ***
logic MDUE; // Multiply/divide instruction
controller c(
.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,

2
pipelined/src/ieu/regfile.sv
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@ -50,7 +50,7 @@ module regfile (
// reset is intended for simulation only, not synthesis
// can logic be adjusted to not need resettable registers?
always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset
always_ff @(negedge clk)
if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
else if (we3) rf[a3] <= wd3;