Moved swap from qslc to otfc

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -32,7 +32,6 @@
 
 module fdivsqrtqsel2 ( 
   input  logic [3:0] ps, pc, 
-  input  logic  swap,
   output logic  up, uz, un
 );
  
@@ -56,11 +55,7 @@ module fdivsqrtqsel2 (
 						(ps[0]&pc[0])))));
 
   // Produce digit = +1, 0, or -1
-  assign pos = magnitude & ~sign;
+  assign up = magnitude & ~sign;
   assign uz  = ~magnitude;
-  assign neg = magnitude & sign;
-
-  // Check for swap (int div only)
-  assign un = swap ? pos : neg;
-  assign up = swap ? neg : pos;
+  assign un = magnitude & sign;
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv

@@ -34,7 +34,7 @@ module fdivsqrtqsel4cmp (
   input logic [2:0] Dmsbs,
   input logic [4:0] Smsbs,
   input logic [7:0] WSmsbs, WCmsbs,
-  input logic SqrtE, j1, OTFCSwapE, MDUE,
+  input logic SqrtE, j1, MDUE,
   output logic [3:0] udigit
 );
 	logic [6:0] Wmsbs;
@@ -86,12 +86,9 @@ module fdivsqrtqsel4cmp (
  
   // Compare residual W to selection constants to choose digit
   always_comb 
-    if ($signed(Wmsbs) >= $signed(mk2)) udigitsel = 4'b1000; // choose 2
-    else if ($signed(Wmsbs) >= $signed(mk1)) udigitsel = 4'b0100; // choose 1
-    else if ($signed(Wmsbs) >= $signed(mk0)) udigitsel = 4'b0000; // choose 0
-    else if ($signed(Wmsbs) >= $signed(mkm1)) udigitsel = 4'b0010; // choose -1
-    else udigitsel = 4'b0001; // choose -2	
-
-  assign udigitswap = {udigitsel[0], udigitsel[1], udigitsel[2], udigitsel[3]};
-  assign udigit = OTFCSwapE ? udigitswap : udigitsel;
+    if ($signed(Wmsbs) >= $signed(mk2)) udigit = 4'b1000; // choose 2
+    else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1
+    else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0
+    else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1
+    else udigit = 4'b0001; // choose -2	
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -60,7 +60,7 @@ module fdivsqrtstage2 (
 	// 0000 =  0
 	// 0010 = -1
 	// 0001 = -2
-  fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], OTFCSwapE, up, uz, un);
+  fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
 
   // Sqrt F generation
   fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F);
@@ -82,7 +82,7 @@ module fdivsqrtstage2 (
   assign CNext = {1'b1, C[`DIVb+1:1]};
 
   // Unified On-The-Fly Converter to accumulate result
-  fdivsqrtuotfc2 uotfc2(.up, .uz, .C(CNext), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc2 uotfc2(.up, .un, .swap(OTFCSwapE), .C(CNext), .U, .UM, .UNext, .UMNext);
 endmodule
 
 

pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -65,7 +65,7 @@ module fdivsqrtstage4 (
   assign WCmsbs = WC[`DIVb+3:`DIVb-4];
   assign WSmsbs = WS[`DIVb+3:`DIVb-4];
 
-  fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .OTFCSwapE, .MDUE);
+  fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit, .MDUE);
   assign un = 1'b0; // unused for radix 4
 
   // F generation logic
@@ -94,7 +94,7 @@ module fdivsqrtstage4 (
   assign CNext = {2'b11, C[`DIVb+1:2]};
  
   // On-the-fly converter to accumulate result
-  fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtE), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .swap(OTFCSwapE), .Sqrt(SqrtE), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
 endmodule
 
 

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -34,7 +34,7 @@
 // Unified OTFC, Radix 2 //
 ///////////////////////////////
 module fdivsqrtuotfc2(
-  input  logic         up, uz,
+  input  logic         up, un, swap,
   input  logic [`DIVb+1:0] C,
   input logic [`DIVb:0] U, UM,
   output logic [`DIVb:0] UNext, UMNext
@@ -42,20 +42,24 @@ module fdivsqrtuotfc2(
   //  The on-the-fly converter transfers the divsqrt
   //  bits to the quotient as they come.
   logic [`DIVb:0] K;
+  logic unSwap, upSwap;
+  
+  // Check for swap (int div only)
+  assign unSwap = swap ? up : un;
+  assign upSwap = swap ? un : up;
 
   assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1));
 
   always_comb begin
-    if (up) begin
+    if (upSwap) begin
       UNext  = U | K;
       UMNext = U;
-    end else if (uz) begin
-      UNext  = U;
-      UMNext = UM | K;
-    end else begin        // If up and uz are not true, then un is
+    end else if (unSwap) begin
       UNext  = UM | K;
       UMNext = UM;
-    end 
+    end else begin // If up and un are not true, then uz is
+      UNext  = U;
+      UMNext = UM | K;
+    end
   end
-
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -32,7 +32,7 @@
 
 module fdivsqrtuotfc4(
   input  logic [3:0]   udigit,
-  input  logic         Sqrt,
+  input  logic         Sqrt, swap,
   input  logic [`DIVb:0] U, UM,
   input  logic [`DIVb:0] C,
   output logic [`DIVb:0] UNext, UMNext
@@ -41,25 +41,29 @@ module fdivsqrtuotfc4(
   //  bits to the quotient as they come.
   //  Use this otfc for division and square root.
 
+  logic [3:0] udigitswap, udigitsel;
   logic [`DIVb:0] K1, K2, K3;
   assign K1 = (C&~(C << 1));        // K
   assign K2 = ((C << 1)&~(C << 2)); // 2K
   assign K3 = (C & ~(C << 2));      // 3K
 
+  assign udigitswap = {udigit[0], udigit[1], udigit[2], udigit[3]};
+  assign udigitsel = swap ? udigitswap : udigit;
+
   always_comb begin
-    if (udigit[3]) begin
+    if (udigitsel[3]) begin           // +2
       UNext  = U | K2;
       UMNext = U | K1;
-    end else if (udigit[2]) begin
+    end else if (udigitsel[2]) begin  // +1
       UNext  = U | K1;
       UMNext = U;
-    end else if (udigit[1]) begin
+    end else if (udigitsel[1]) begin  // -1
       UNext  = UM | K3;
       UMNext = UM | K2;
-    end else if (udigit[0]) begin
+    end else if (udigitsel[0]) begin  // -2
       UNext  = UM | K2;
       UMNext = UM | K1;
-    end else begin        // udigit = 0
+    end else begin                    // 0
       UNext  = U;
       UMNext = UM | K3;
     end