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Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.

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The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
This commit is contained in:
Ross Thompson 2022-10-11 10:47:13 -05:00
parent 36c0e1d4e9
commit 403daecc8e
5 changed files with 9 additions and 9 deletions
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6
pipelined/config/rv32i/wally-config.vh
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@ -88,11 +88,11 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 1'b1
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h07FFFFFF
`define DTIM_RANGE 34'h000007FF
`define IROM_SUPPORTED 1'b1
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h07FFFFFF
`define BOOTROM_SUPPORTED 1'b1
`define IROM_RANGE 34'h000007FF
`define BOOTROM_SUPPORTED 1'b0
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF
`define UNCORE_RAM_SUPPORTED 1'b0

4
pipelined/config/rv32ic/wally-config.vh
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@ -87,10 +87,10 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 1'b1
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h007FFFFF
`define DTIM_RANGE 34'h00000FFF
`define IROM_SUPPORTED 1'b1
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h007FFFFF
`define IROM_RANGE 34'h00003FFF
`define BOOTROM_SUPPORTED 1'b0
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF

4
pipelined/config/rv64i/wally-config.vh
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@ -94,10 +94,10 @@
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define DTIM_SUPPORTED 1'b1
`define DTIM_BASE 56'h80000000
`define DTIM_RANGE 56'h007FFFFF
`define DTIM_RANGE 56'h000007FF
`define IROM_SUPPORTED 1'b1
`define IROM_BASE 56'h80000000
`define IROM_RANGE 56'h007FFFFF
`define IROM_RANGE 56'h000007FF
`define BOOTROM_SUPPORTED 1'b0
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF

2
pipelined/regression/wally-pipelined-batch.do
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@ -76,7 +76,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
run -all
# power off -r /dut/core/*
} else {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 +define+DTIM_RANGE=8388607 +define+IROM_RANGE=8388607
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt

2
pipelined/regression/wally-pipelined.do
View File

@ -79,7 +79,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
if {$2 eq "ahb"} {
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
} else {
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+DTIM_RANGE=8388607 +define+IROM_RANGE=8388607
}
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt