Removed unused signals in FPU and CSR

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -42,7 +42,6 @@ module fdivsqrt(
   input  logic XNaNE, YNaNE, 
   input  logic FDivStartE, IDivStartE,
   input  logic StallM,
-  input  logic StallE,
   input  logic FlushE,
   input  logic SqrtE, SqrtM,
 	input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
@@ -74,17 +73,17 @@ module fdivsqrt(
     .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
     .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, 
     .nE, .nM, .mM, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
-    .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
+    .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, .nE,
-    .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ 
+    .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallM, .FlushE, /*.DivDone, */ 
     .XZeroE, .YZeroE, .AZeroE, .BZeroE,
     .XNaNE, .YNaNE, .MDUE,
     .XInfE, .YInfE, .WZeroM, .SpecialCaseM);
   fdivsqrtiter fdivsqrtiter(
     .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
     .X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
-    .IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwapE,
+    .IFDivStartE, .OTFCSwapE,
     .FDivBusyE);
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -41,7 +41,6 @@ module fdivsqrtfsm(
   input  logic FDivStartE, IDivStartE,
   input  logic XsE,
   input  logic SqrtE,
-  input  logic StallE,
   input  logic StallM,
   input  logic FlushE,
   input  logic WZeroM,
@@ -117,9 +116,9 @@ module fdivsqrtfsm(
           if (SpecialCaseE) state <= #1 DONE;
           else             state <= #1 BUSY;
       end else if (state == BUSY) begin
-          if (step == 1)  state <= #1 DONE;
+          if (step == 1 | WZeroM)  state <= #1 DONE; // terminate early when residual is zero
           step <= step - 1;
-      end else if ((state == DONE) | (WZeroM & (state == BUSY))) begin
+      end else if ((state == DONE)) begin
         if (StallM) state <= #1 DONE;
         else        state <= #1 IDLE;
       end 

pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -34,8 +34,6 @@ module fdivsqrtiter(
   input  logic clk,
   input  logic IFDivStartE, 
   input  logic FDivBusyE, 
-  input  logic [`NE-1:0] Xe, Ye,
-  input  logic XZeroE, YZeroE, 
   input  logic SqrtE, MDUE,
 //  input  logic SqrtM,
   input  logic OTFCSwapE,
@@ -64,7 +62,6 @@ module fdivsqrtiter(
   logic [`DIVb+3:0]      WSN, WCN;               // Q4.b
   logic [`DIVb+3:0]      DBar, D2, DBar2;        // Q4.b
   logic [`DIVb+1:0]      NextC;
-  logic [`DIVb+1:0]      CMux;
   logic [`DIVb:0]        UMux, UMMux;
   logic [`DIVb:0]        initU, initUM;
   /* verilator lint_on UNOPTFLAT */
@@ -94,8 +91,8 @@ module fdivsqrtiter(
   logic [1:0] initCUpper;
   assign initCUpper = (SqrtE & ~(MDUE)) ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
   assign initC = {initCUpper, {`DIVb{1'b0}}};
-  mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, CMux); 
-  flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, CMux, C[0]);
+  mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
+  flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
 
    // Divisior register
   flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -125,7 +125,7 @@ module fdivsqrtpostproc(
       IntRemM  = NormRemM;
     end 
   
-  always_comb
+  always_comb  // could merge into postprocessor shifter
     if (RemOpM) begin
       NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
       PreResultM = IntRemM;

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -39,7 +39,7 @@ module fdivsqrtpreproc (
   input  logic Sqrt,
   input  logic XZeroE,
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-	input  logic [2:0] 	Funct3E, Funct3M,
+	input  logic [2:0] 	Funct3E,
 	input  logic MDUE, W64E,
   output logic [`DIVBLEN:0] nE, nM, mM,
   output logic OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,

pipelined/src/fpu/fma/fma.sv

@@ -84,7 +84,7 @@ module fma(
     // // Addition/LZA
     // ///////////////////////////////////////////////////////////////////////////////
         
-    fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
+    fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
 
     fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
 endmodule

pipelined/src/fpu/fma/fmaadd.sv

@@ -33,8 +33,8 @@
 module fmaadd(
     input logic  [3*`NF+5:0]    Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
     input logic  [2*`NF+1:0]    Pm,       // the product's mantissa
-    input logic                 Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
-    input logic                InvA,          // invert the aligned addend
+    input logic                 Ps,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
+    input logic                 InvA,          // invert the aligned addend
     input logic                 KillProd,      // should the product be set to 0
     input logic                 ZmSticky,
     input logic  [`NE-1:0]      Ze,

pipelined/src/fpu/fpu.sv

@@ -91,7 +91,6 @@ module fpu (
    logic 		      XsE, YsE, ZsE;                // input's sign - execute stage
    logic 		      XsM, YsM;                       // input's sign - memory stage
    logic [`NE-1:0] 	XeE, YeE, ZeE;                // input's exponent - execute stage
-   logic [`NE-1:0] 	ZeM;                              // input's exponent - memory stage
    logic [`NF:0] 	   XmE, YmE, ZmE;                // input's fraction - execute stage
    logic [`NF:0] 	   XmM, YmM, ZmM;                // input's fraction - memory stage
    logic 		      XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
@@ -265,7 +264,7 @@ module fpu (
    fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
                   .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
                   .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
-                  .StallE, .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
+                  .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
                   .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
 
                   //
@@ -343,7 +342,6 @@ module fpu (
 
    flopenrc #(`NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
    flopenrc #(`NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
-   flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
    flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
    flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
    flopenr #(15) EMFpReg5 (clk, reset, ~StallUnpackedM, 
@@ -372,7 +370,7 @@ module fpu (
 
    assign FpLoadStoreM = FResSelM[1];
 
-   postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
+   postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
                            .FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
                            .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
                            .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),

pipelined/src/fpu/postproc/divshiftcalc.sv

@@ -32,8 +32,7 @@
 
 module divshiftcalc(
     input logic  [`DIVb:0] DivQm,
-    input logic  [`FMTBITS-1:0] Fmt,
-    input logic Sqrt,
+    input logic Sqrt, // *** not used right now.  Maybe merge with shift from postprocess
     input logic [`NE+1:0] DivQe,
     output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt,
     output logic [`NORMSHIFTSZ-1:0] DivShiftIn,

pipelined/src/fpu/postproc/fmashiftcalc.sv

@@ -31,7 +31,6 @@
 
 module fmashiftcalc(
     input logic  [3*`NF+5:0]            FmaSm,       // the positive sum
-    input logic  [`NE-1:0]              Ze,      // exponent of Z
     input logic  [$clog2(3*`NF+7)-1:0]  FmaSCnt,   // normalization shift count
     input logic  [`FMTBITS-1:0]         Fmt,       // precision 1 = double 0 = single
     input logic [`NE+1:0] FmaSe,

pipelined/src/fpu/postproc/postprocess.sv

@@ -33,7 +33,6 @@
 module postprocess (
     // general signals
     input logic                             Xs, Ys,  // input signs
-    input logic  [`NE-1:0]                  Ze, // input exponents
     input logic  [`NF:0]                    Xm, Ym, Zm, // input mantissas
     input logic  [2:0]                      Frm,       // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
     input logic  [`FMTBITS-1:0]             Fmt,       // precision 1 = double 0 = single
@@ -146,9 +145,9 @@ module postprocess (
 
     cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn,  
                               .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
-    fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
+    fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
                           .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
-    divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn);
+    divshiftcalc divshiftcalc(.Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn);
 
     always_comb
         case(PostProcSel)

pipelined/src/privileged/csr.sv

@@ -199,7 +199,7 @@ module csr #(parameter
   // CSRs
   ///////////////////////////////////////////
 
-  csri   csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, 
+  csri   csri(.clk, .reset, .InstrValidNotFlushedM, 
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
               .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
@@ -219,7 +219,7 @@ module csr #(parameter
               .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
               .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
               .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
-  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW,
+  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM,
               .CSRMWriteM, .MTrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
               .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
@@ -227,7 +227,7 @@ module csr #(parameter
               .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
               .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
               .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
-  csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM, .StallW,
+  csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM,
               .CSRSWriteM, .STrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
               .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
@@ -235,7 +235,7 @@ module csr #(parameter
               .SCOUNTEREN_REGW,
               .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
               .WriteSSTATUSM, .IllegalCSRSAccessM);
-  csru  csru(.clk, .reset, .InstrValidNotFlushedM, .StallW,
+  csru  csru(.clk, .reset, .InstrValidNotFlushedM,
               .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
               .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
               .IllegalCSRUAccessM);

pipelined/src/privileged/csri.sv

@@ -38,7 +38,7 @@ module csri #(parameter
     SIP = 12'h144
   ) (
     input logic 			clk, reset, 
-    input logic 			InstrValidNotFlushedM, StallW,
+    input logic 			InstrValidNotFlushedM, 
     input logic 			CSRMWriteM, CSRSWriteM,
     input logic [`XLEN-1:0] CSRWriteValM,
     input logic [11:0] 		CSRAdrM,

pipelined/src/privileged/csrm.sv

@@ -72,7 +72,7 @@ module csrm #(parameter
     MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
   ) (
     input logic 	     clk, reset, 
-    input logic 	     InstrValidNotFlushedM, StallW,
+    input logic 	     InstrValidNotFlushedM, 
     input logic 	     CSRMWriteM, MTrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,

pipelined/src/privileged/csrs.sv

@@ -50,7 +50,7 @@ module csrs #(parameter
 
   ) (
     input logic 	     clk, reset, 
-    input logic 	     InstrValidNotFlushedM, StallW,
+    input logic 	     InstrValidNotFlushedM, 
     input logic 	     CSRSWriteM, STrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, 

pipelined/src/privileged/csrsr.sv

@@ -32,7 +32,8 @@
 `include "wally-config.vh"
 
 module csrsr (
-  input  logic             clk, reset, StallW,
+  input  logic             clk, reset, 
+  input  logic             StallW,
   input  logic             WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM, 
   input  logic             TrapM, FRegWriteM,
   input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,

pipelined/src/privileged/csru.sv

@@ -37,7 +37,7 @@ module csru #(parameter
   FRM = 12'h002,
   FCSR = 12'h003) (
     input  logic             clk, reset, 
-    input  logic             InstrValidNotFlushedM, StallW,
+    input  logic             InstrValidNotFlushedM,
     input  logic             CSRUWriteM,
     input  logic [11:0]      CSRAdrM,
     input  logic [`XLEN-1:0] CSRWriteValM,