forked from Github_Repos/cvw
Removed NonIROM and NonDTIM select signals from IFU and LSU.
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cc1ba84637
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0fb45cffa1
@ -92,7 +92,7 @@ module ifu (
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logic CompressedF;
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logic [31:0] InstrRawD, InstrRawF;
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logic [31:0] FinalInstrRawF;
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logic [1:0] NonIROMMemRWM;
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logic [1:0] RWF;
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logic [31:0] InstrE;
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logic [`XLEN-1:0] PCD;
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@ -113,7 +113,6 @@ module ifu (
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logic BusStall;
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logic ICacheStallF, IFUCacheBusStallF;
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logic CPUBusy;
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logic SelIROM;
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(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
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// branch predictor signal
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logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F;
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@ -193,13 +192,11 @@ module ifu (
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assign IROMAdr = CPUBusy | reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
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/* verilator lint_on WIDTH */
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adrdec iromdec(PCFExt, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM);
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//assign NonIROMMemRWM = {~SelIROM, 1'b0};
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assign NonIROMMemRWM = 2'b10;
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assign RWF = 2'b10;
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irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
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end else begin
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assign SelIROM = 0; assign NonIROMMemRWM = 2'b10;
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assign RWF = 2'b10;
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end
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if (`BUS) begin : bus
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localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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@ -213,7 +210,7 @@ module ifu (
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logic [1:0] CacheRW, RW;
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assign CacheRW = {ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF};
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assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
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assign RW = RWF & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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@ -227,7 +224,7 @@ module ifu (
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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.ByteMask('0), .WordCount('0), .SelBusWord('0),
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.FinalWriteData('0),
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.RW(NonIROMMemRWM),
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.RW(RWF),
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.Atomic('0), .FlushCache('0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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@ -249,7 +246,7 @@ module ifu (
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assign IFUHADDR = PCPF;
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logic CaptureEn;
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logic [1:0] RW;
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assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
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assign RW = RWF & ~{ITLBMissF, ITLBMissF};
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assign IFUHSIZE = 3'b010;
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ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
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@ -130,7 +130,7 @@ module lsu (
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM(NonDTIMMemRWM), .AtomicM, .ITLBMissF, .ITLBWriteF,
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .SelReplay,
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.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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@ -140,7 +140,7 @@ module lsu (
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.IgnoreRequestTLB);
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end else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign CPUBusy = StallW; assign PreLSURWM = NonDTIMMemRWM;
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assign CPUBusy = StallW; assign PreLSURWM = MemRWM;
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assign IHAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign IMWriteDataM = WriteDataM;
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@ -207,7 +207,6 @@ module lsu (
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if (`DTIM_SUPPORTED) begin : dtim
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logic [`PA_BITS-1:0] DTIMAdr;
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logic DTIMAccessRW;
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logic MemStage;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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@ -216,11 +215,6 @@ module lsu (
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assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
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assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
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/* verilator lint_on WIDTH */
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assign DTIMAccessRW = |MemRWM;
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// *** Ross remove this.
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adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu?
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//assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected
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assign NonDTIMMemRWM = MemRWM; // *** fix
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dtim dtim(.clk, .reset, .MemRWM,
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.Adr(DTIMAdr),
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